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| yootis | Is there an easy way to generate verilog of litescope and the UART interface so I can insert it into a verilog-only design? | 05:36 |
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| pftbest | Hello. I have some questions about ethernet in litex | 21:43 |
| pftbest | When I add self.add_etherbone(phy, ip, mac) I should be able to ping the board right? because with_icmp is True by default? | 21:44 |
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