| awordnot | and do you have an easy way to scope the chip select pin? | 00:00 |
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| awordnot | maybe someone else can offer some more insight, but to me everything looks fine | 00:01 |
| tpearson-mobile | OK. If it seems good, I'll start digging into it then | 00:01 |
| tpearson-mobile | awordnot: one thing I do find very irritating though about Migen (besides the verbosity (seriously, self.comb(foo.eq(bar)) vs foo = bar??) is I can't do my normal "assign debug_out = some_output_pad" | 00:03 |
| tpearson-mobile | so then you end up wasting a bunch of time trying to get physical probes onto certain signals where the FPGA is normally perfectly able to probe its own internal logic. | 00:03 |
| tpearson-mobile | feels a bit like going back to the stone age :) | 00:03 |
| tpearson-mobile | if I'm missing some way to do that, I'm all ears | 00:04 |
| awordnot | you can access the pads' signals using e.x. platform.request("spiflash4x").miso and add normal comb domain assignments to/from it | 00:04 |
| tpearson-mobile | will that work though if it's driven by another module? when I tried it, it was causing problems, and digging into it the signals were being set to input | 00:05 |
| tpearson-mobile | always possible I was doing something slightly wrong, of course, so if it's supposed to work I'll give it another try | 00:05 |
| awordnot | it should work regardless, but if it's being driven by another module you can just access that module's signal directly | 00:06 |
| tpearson-mobile | well, in this case, it's being driven by the SPI module, so I'd have to dig into that in some other repo -- not the easiest thing to do | 00:06 |
| tpearson-mobile | I'll give direct attach another try | 00:06 |
| awordnot | yeah, i've done the direct attach method a couple of times and it worked fine | 00:07 |
| tpearson-mobile | I will say I'm surprised at the SPI module handling of whatever is going wrong -- spitting back the lowest address byte in the data stream is not what I expected, 0xff or 0x00 was expected in that case.... | 00:07 |
| tpearson-mobile | awordnot: Ah, here's why it doesn't work: "ERROR: Pin B of TRELLIS_IO 'TRELLIS_IO_21' connected to more than a single top level IO.ERROR: Packing design failed" | 00:28 |
| tpearson-mobile | normally I'd tap into the input line to work around that (since input is always working even if the pin is in output mode) but in this case, I'm not sure if there's an easy way to tap into all the abstractions to get at the signal I want | 00:29 |
| felix_ | i wouldn't call the two flash chips nearly identical. 128MBit is 3 byte addressing; more than that needs 4 byte addressing or some other mode where the 4th byte is set via a separate command. might be part of the issue | 00:30 |
| tpearson-mobile | felix_: Oh, no 4 byte addressing on that controller? | 00:35 |
| tpearson-mobile | hrm | 00:36 |
| tpearson-mobile | yeah, that would mean different command sets.... | 00:36 |
| tpearson-mobile | still, it should be failing in a bit of a different manner than what I'm seeing if that was the only issue | 00:37 |
| felix_ | good question; never used it with spi flashes > 16MByte | 00:37 |
| felix_ | yeah | 00:37 |
| tpearson-mobile | well, I'm going to see if we at least get CS# assert or not | 00:37 |
| tpearson-mobile | if so, it can be modified of course for 4BA, it's not *that* difficult | 00:38 |
| tpearson-mobile | I suspect we're dealing with an independent issue though at the moment | 00:38 |
| tpearson-mobile | I guess I kind of assumed it would have a 4BA option given some of the other extras on it like dummy cycle / QSPI support | 00:40 |
| tpearson-mobile | Interestingly there is a "addr_width" variable, hardcoded to 24 | 00:43 |
| tpearson-mobile | I'll probably end up un-hardcoding that and submitting a PR | 00:43 |
| tpearson-mobile | it's strange because so much of the code is autogenerated / dynamic, having that hardcode is almost out of place... | 00:43 |
| tpearson-mobile | Huh. Re-synthesizing the design fixed the pattern weirdness | 00:46 |
| tpearson-mobile | I'm not even going to bother tracking that down, but yes, 4BA is something I have to add | 00:46 |
| tpearson-mobile | considering it's past dinner though that's waiting for another day :) | 00:47 |
| tpearson-mobile | thanks all! | 00:47 |
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| futarisIRCcloud | dkozel: When are you doing gr-verilog on bigbluebutton? | 10:28 |
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| dkozel | futarisIRCcloud: Not sure. Been tangled in mentoring a lot of students who are all starting their summer FOSS projects this week | 12:19 |
| dkozel | also miek has published a proof of concept cxxrtl GNU Radio module which doubles my desire to get that functionality in before pointing more people at gr-verilog | 12:20 |
| dkozel | oh, hi miek :P Didn't realize you were in here | 12:21 |
| dkozel | Also been debugging GNU Radio Anaconda issues. Apparently lots of the FOSS FPGA toolchains are going to end up packaged according to mithro | 12:22 |
| dkozel | It'd also be great to have gr-verilog packaged there with all it's dependencies, it'd make it accessible outside of Linux | 12:22 |
| miek | hi :) | 12:22 |
| dkozel | I'm so pleased you got that working! | 12:23 |
| keesj | hmm gr-verilog? running on the plutoSDR? | 12:24 |
| dkozel | keesj: Just on a host. It's for including HDL in a GNU Radio flowgraph, running in a simulation backend (Verilator now, cxxrtl soon) | 12:26 |
| dkozel | But as a bridge to gr-litex, being able to build accelerator gatewares from a flowgraph (partially working) | 12:27 |
| tnt | Does cxxrtl (or verilator) work with the Xilinx simulation models ? (for DSP / BRAM / ...) | 12:28 |
| dkozel | I have no idea. I've never used a Xilinx model for anything | 12:28 |
| tnt | No synthesis tool can infer complex DSP function they can do, so if you want to actually use the fpga to its potential you don't really have a choice. | 12:29 |
| keesj | verilator not not even the ice40 pll | 12:30 |
| keesj | you will need to implement a simlator for the testing part (I think) | 12:31 |
| dkozel | I don't really care about using the FPGA to it's potential at this point. Getting even a basic implementation together has a lot of value in teaching situations. | 12:38 |
| dkozel | Also I think this is a stepping stone. The tooling is improving and even without the Xilinx models (which it looks like Verilator at least partially can handle) I'm guessing (and it is a guess) that there's useful DSP that can be written | 12:39 |
| dkozel | even if it turns out to be impractical, this is already a good learning experience for me. I didn't have anything I wanted to do after blinking an LED :) | 12:40 |
| keesj | Haha.. yea. one thing I really enjoyed was reading https://www.amazon.com/gp/product/1728619440/ref=as_li_tl?ie=UTF8&camp=1789&creative=9325&creativeASIN=1728619440&linkCode=as2&tag=pzp-20&linkId=c149f6365c0a676065eb6d7c5f8dd6ae and playing with https://8bitworkshop.com/v3.5.1/?platform=verilog&file=test_hvsync.v | 12:42 |
| tpb | Title: 8bitworkshop IDE (at 8bitworkshop.com) | 12:42 |
| keesj | Generating a VGA signal is a pretty cool experience specially if you hook it up to a screen. | 12:43 |
| dkozel | :) My goal is to generate an FSK signal so I can hook it up to a radio | 12:44 |
| keesj | then porting that code to litex/migen might be also cool | 12:44 |
| dkozel | I have the loopback/passthrough running in LiteX+GNU Radio, on the Artix 7, over litepcie and Thunderbolt 3. | 12:45 |
| keesj | do you want to generate the data in binary (e.g. i q signals) or .. like .. generate/emulate an analog signal? | 12:45 |
| dkozel | All I need to do now is write the wishbone module and figure out how to route the litepcie data to the custom block and back | 12:46 |
| dkozel | IQ uint16s | 12:46 |
| keesj | that is pretty cool | 12:46 |
| dkozel | uint16 (not signed) :P | 12:46 |
| dkozel | Should be fun. And I have a larger FPGA coming soon so need to get on with this small one before then :P | 12:47 |
| keesj | At FOSDEM .. 2 or 3 years ago there was reseacher that did .. something like that but I think the code was running on the SDR itself. the way you use it the block is really standalone (with input and output) or does it have the full flowgraph on the board? | 12:49 |
| keesj | (I think the FPGA was doing mostly FFT) | 12:49 |
| dkozel | This is still just one sub-graph running on the FPGA and the main runtime is on a host | 12:49 |
| keesj | https://www.youtube.com/watch?v=rns3WTU4S5s | 12:50 |
| daveshah | tnt: there is a DSP48E1 model in Yosys that should work with cxxrtl. It has been verified against the sim model in Xilinx so should be correct | 12:51 |
| dkozel | We have a huge amount of work going right now (part of why I'm not able to put time into this project) on redoing the runtime to natively support heterogeneous platforms, including auto building gateware and GPU DSP | 12:51 |
| dkozel | but that's probably a conversation better had on #gnuradio-dev. I don't want to wander this channel | 12:51 |
| keesj | yea sorry | 12:51 |
| tnt | daveshah: interesting thanks ! | 12:55 |
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| daveshah | What is still missing is a ram model, iirc | 12:56 |
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| mithro | dkozel: Yes -> https://docs.google.com/document/d/1BZcSzU-ur0J02uO5FSGHdJHYGnRfr4n4Cb7PMubXOD4/edit#heading=h.ee3kfes8c7nu and https://github.com/litex-hub?q=litex-conda&type=&language= | 16:40 |
| tpb | Title: EDDA - Conda based system for FPGA and ASIC Dev - Google Docs (at docs.google.com) | 16:40 |
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