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| _florent_ | thanks for looking at this somlo, zyp. That's also a bit out of my confort zone, but could try to help. We could use the simulation with verilator to reproduce the issue and fix it correctly on at least one CPU first (running a simulation with SERV or Vexriscv is just a few seconds) and i could apply the change to the others CPU. | 05:26 |
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| zyp | somlo, how did it go? | 06:44 |
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| zyp | I fixed the CRC code as well and am building for vexriscv now | 07:18 |
| zyp | fun, that broke everything because apparently the BIOS for vexriscv adds a .got section | 07:47 |
| zyp | I've got a solution that appears to work on vexriscv now, I'll spend some time looking at the other cpus as well and then submit a PR | 08:52 |
| zyp | but I've got some errands to run before that, so it might be a while | 08:52 |
| benh | right I noticed our .lds might need to be enriched to support more sections | 08:54 |
| benh | .got comes to mind | 08:55 |
| benh | the kernel is a good example of how messy it can get :) | 08:55 |
| benh | some archs might have a .toc or .opd | 08:57 |
| somlo | zyp: commenting out the crc function allowed the bios to proceed, but then it went on to print out a bunch of garbage and eventually crash | 09:36 |
| somlo | printf says content (at least first 16 bytes) starting at 0x10008600 are not the same as content starting at 0x11000000 | 09:37 |
| somlo | gotta be afk for a few hours, bbl | 09:37 |
| zyp | I tried --cpu-type rocket, but litex is failing with this: https://paste.jvnv.net/view/dsI8G | 11:17 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 11:17 |
| zyp | apparently it wants to connect a 64-bit cpu port to a 128-bit memory port, and upconversion is not supported | 11:18 |
| zyp | okay, --cpu-variant linuxd solves that | 11:34 |
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| zyp | appears to work perfectly here on both vexriscv and rocket now: https://paste.jvnv.net/view/WFsom | 12:15 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 12:15 |
| benh | Memspeed Writes: 1047Mbps Reads: 1051Mbps | 12:49 |
| benh | :-) | 12:49 |
| benh | Microwatt's getting there ... (standalone MW with a full 64-bit pipelined wishbone and my L2 cache) | 12:49 |
| benh | hopefully we'll get that in LiteX soon | 12:49 |
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| somlo | zyp: mind posting a patch (or sending a PR, and linking issue #566)? | 13:27 |
| zyp | I'll do a PR, but I'm looking at having a go at all the other cpus as well | 13:29 |
| zyp | benh, as far as I can tell, microwatt/crt0.S doesn't even set up .bss, is that correct? | 13:46 |
| keesj | what is microwatt? | 14:09 |
| keesj | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/microwatt/core.py | 14:09 |
| tpb | Title: litex/core.py at master · enjoy-digital/litex · GitHub (at github.com) | 14:09 |
| keesj | wow.. it is vhdl code | 14:10 |
| keesj | (just had a 4 days advanced security training using FPGA / verilog) https://advancedsecurity.training/training/live-fpga-hacking . I became better a verilog but.well.. | 14:13 |
| keesj | I also tried to do the assignments with litex (parts of them) but I was kinda lacking a UART RX/TX block that is simple enough to mess arround with (not one to access via wishbone or .. to complicated) | 14:14 |
| keesj | and the second "problem" I had (that I solved) was when using additional pins bit is just a little bit cumbersome if you are trying to prove "litex is much better" | 14:15 |
| zyp | somlo, https://github.com/enjoy-digital/litex/pull/567 | 14:41 |
| tpb | Title: bios/linker: Place .data in sram with initial copy in rom. by zyp · Pull Request #567 · enjoy-digital/litex · GitHub (at github.com) | 14:41 |
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| somlo | zyp: thanks! I tried, it, but it's printing garbage to the terminal for me (starting with the sdram initialization output), then eventually hangs | 16:19 |
| somlo | well, if I don't try to boot from sdcard it works (boots from ethernet) | 16:20 |
| somlo | so I think we're on the right track, just not 100% there yet | 16:21 |
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| Dolu | futarisIRCcloud, about the DMIPS in linux. One big issue is currently that the strcmp used for userspace is a stupid loop which check one byte at the time, instead of the word based one which is used in barmetal/newlib | 17:03 |
| Dolu | So, in barmetal, the CPU configuration used is about 1.1 or 1.2 DMIPS/Mhz | 17:06 |
| Dolu | (baremetal => not the same libc => optimized strcmp) | 17:07 |
| Dolu | Not sure if that was strcmp or strlen XD, but one of those function was realy dumply implemented in the linux libc | 17:08 |
| Dolu | Then about the memory speed, in addition of what florent said, there is also the fact that the i$ bus is 128 bits wide / d$ bus is 64 bits wide on the SMP cluster. On the single core version they are both only 32 bits wide, which result into high cache miss penality (transfer time) | 17:13 |
| zyp | somlo, I wonder if the problem is that putting .data in sram leaves less room for the stack, so stack grows into .bss | 17:22 |
| zyp | somlo, any chance you could try simply increasing sram size? | 17:22 |
| zyp | worst case we rule out that as an issue | 17:23 |
| somlo | zyp: trying now (it's only 4k by default, trying 32k). If that works, I'll have to also try this whole thing on an 85k ecp5 board, there might be less wiggle room there... | 17:35 |
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| zyp | if 4k is too little, it's probably enough to increase by one block or so, as far as I can tell .data itself tends to be less than 1k | 18:06 |
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| zyp | it was 776B in the bios.elf you sent me yesterday | 18:07 |
| Dolu | There is a past bin with the two version of memcmp : https://pastebin.com/QL9CSuF6 . Quite some difference. I'm now mesuring in a simulation the drhystone run, to be sure there is not something else hidden. | 18:08 |
| tpb | Title: [M68000 Assembler] linux libc : 0007764c : 7764c: 00150513 add - Pastebin.com (at pastebin.com) | 18:08 |
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| somlo | zyp: works like a charm with 8x the default :) | 18:32 |
| somlo | we should come up with a reasonable number for the new default, maybe incorporate that into the PR with a note in the commit blurb | 18:33 |
| somlo | probably doubling it to 8k will work, I can try it now that my knee-jerk "make it BIG" thing has panned out :) | 18:34 |
| zyp | if it worked at 4k before, I'm confident it'd work at 6k now, unless it actually had a collision before as well that just didn't show any symptoms | 18:35 |
| zyp | but yeah, 8k is a rounder number | 18:35 |
| zyp | .data and .bss are easy to find the requirements for, since you can just read those right from the elf header, but stack usage is harder | 18:37 |
| zyp | I did some experiments many years ago extracting function stack frame and call tree information from gcc to find the maximum stack usage, but as soon as you have any indirect calls, building a complete call tree gets pretty hard | 18:40 |
| somlo | the default setting is pretty self-contained, here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L78 and here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L267 | 18:40 |
| tpb | Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com) | 18:40 |
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| somlo | zyp: doubling sram works (is sufficient). Would you mind pushing an additional commit to PR #567 to modify the default in soc_core.py? | 19:15 |
| zyp | sure, only need to change those two places? | 19:15 |
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| somlo | that's where the default comes from on every target's command line, as far as I can tell | 19:17 |
| zyp | done | 19:18 |
| somlo | zyp: cool beans, I changed my hacky workaround for the global variable to let it remain in .data :) | 19:36 |
| zyp | great, now we just need the two last cpus fixed as well | 19:39 |
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| Dolu | futarisIRCcloud: I investigated more about the dhrystone package in buildroot and how that's compiled. And basicaly that's shity. It's compiled in -Os instead of -O3, and i can't spot any -fno-inline. Most of the time, the CPU has to run into strcpy and strcmp which are pretty bad compared to the bar metal version. | 21:49 |
| Dolu | with the SoC in baremetal, you should get about 1.08 DMIPS/Mhz, i turned off quite some feature while i was trying to boost the cluster frequancy (should be able to go up to 125 Mhz with some margin) | 21:58 |
| zyp | -Os doesn't tend to be too bad though, it's -O2 with a few speed for size tradeoffs | 22:12 |
| Dolu | zyp: In that specific case, that's prety bad, basicaly, the strcpy of the benchmark is using 200 instructions per benchmark loop, instead of 20. On bar metal, one benchmark loop is 322 instructions. | 22:27 |
| zyp | fair enough | 22:28 |
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| tpearson-mobile | So I'm trying to use the SpiFlash peripheral in MMIO mode with a Micron SPI part | 23:27 |
| tpearson-mobile | when I try to do a dump of the MMIO space, all I get is 0xa0000000 00 00 00 00 44 44 44 44 88 88 88 88 cc cc cc cc | 23:27 |
| tpearson-mobile | 0xa0000010 00 00 00 00 44 44 44 44 88 88 88 88 cc cc cc cc ....DDDD........ | 23:27 |
| tpearson-mobile | etc. | 23:27 |
| tpearson-mobile | obviously I'm missing something, any hints? :) | 23:28 |
| tpearson-mobile | is this what the peripheral does when it can't talk to an external SPI (it does the same thing with the SPI pins completely disconnected, FWIW) or is this a more fundamental problem with the SoC configuration? | 23:29 |
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| awordnot | tpearson-mobile: which flash part are you using? Looking at the SpiFlash peripherals' code it seems like they only support spi mode 3 so the part will need to support that | 23:49 |
| tpearson-mobile | yeah it supports mode 3 | 23:50 |
| tpearson-mobile | N25Q512 | 23:50 |
| tpearson-mobile | nearly identical to the N25Q128 that's already on the Versa board | 23:50 |
| awordnot | and you're sure you're looking at the right MMIO address range? | 23:51 |
| tpearson-mobile | should be, yeah | 23:51 |
| tpearson-mobile | mem_map = { "hostspiflash": 0xa0000000, } | 23:51 |
| tpearson-mobile | and "mr 0xa0000000 32" | 23:51 |
| tpearson-mobile | I was honestly expecting tis to "just work" | 23:52 |
| awordnot | hmm, well I don't see anything in the code that would artificially generate that pattern you're seeing (unless I'm missing it) | 23:52 |
| awordnot | which is strange | 23:53 |
| tpearson-mobile | here's the tie in: https://paste.ee/p/lZ9Yw | 23:53 |
| tpb | Title: Paste.ee - View paste lZ9Yw (at paste.ee) | 23:53 |
| tpearson-mobile | and yeah, I'm puzzled | 23:53 |
| awordnot | when you run the soc builder, does your 'hostspiflash' memory region get printed out? | 23:55 |
| tpearson-mobile | INFO:SoCBusHandler:hostspiflash Region added at Origin: 0xa0000000, Size: 0x04000000, Mode: RW, Cached: True Linker: False.INFO:SoCBusHandler:hostspiflash added as Bus Slave.INFO:SoCCSRHandler:hostspiflash CSR allocated at Location 7. | 23:56 |
| awordnot | hmm yeah everything looks good in terms of the SpiFlash instantiation. I guess the next thing to check would be the pinout | 23:59 |
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