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| tpearson-mobile | I'll try the base class approach, though doesn't Python let you override an internal variable of a base class unlike C? | 00:01 |
|---|---|---|
| tpearson-mobile | *C++? | 00:01 |
| awordnot | it does, but looking closer, it seems like CSRStorage/Status will split multi-word variables into bus-sized words, which apparently is 8-bit by default for CSR. Looking into how to set CSR to 32-bit... | 00:02 |
| tpearson-mobile | and "You can zpecify 32-bit wide CSRs but you’ll probably run into compatibility issues with other IP librariers that have hard-coded the 8-bit assumption." -- I'm just shaking my head here. If 32-bit access is allowed, those libraries should be considered to have a bug, not force all of LiteX into a funky sparse address layout | 00:02 |
| somlo | tpearson-mobile, awordnot: on the litex target build command line, add `--csr-data-width=32` :) | 00:03 |
| tpearson-mobile | no modern CPU operates at a byte level for bus access; I'm trying to figure out where in the world that idea came from... | 00:03 |
| awordnot | aha, thank you somlo | 00:03 |
| tpearson-mobile | any way to force it in the target .py file? | 00:03 |
| somlo | python then generates a set of "accessors" in <build-directory>/software/include/generated/csr.h | 00:03 |
| tpearson-mobile | somlo: yes, I saw that, but those are dozens of instructions each | 00:04 |
| tpearson-mobile | on a 75MHz CPU | 00:04 |
| tpearson-mobile | in a heavily used transfer path | 00:04 |
| somlo | that either gather (via shift and or operations) the 8-bit values scattered all over the address space, or read 32 bits at a time, depending on the csr-data-width used | 00:04 |
| tpearson-mobile | doesn't seem like the best idea :) | 00:04 |
| somlo | sometimes you have wider-than-32-bit registers, in which case you still have to shift-and-or, but 32 bits at a time instead of 8 :) | 00:05 |
| awordnot | tpearson-mobile: add 'csr_data_width=32' as a parameter to SoCCore.__init__ in your SoC class to set the default | 00:05 |
| tpearson-mobile | great, thanks! | 00:05 |
| somlo | right now, the behavior is best described by https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/include/hw/common.h | 00:06 |
| tpb | Title: litex/common.h at master · enjoy-digital/litex · GitHub (at github.com) | 00:06 |
| tpearson-mobile | somlo: is there some CPU that LiteX uses that has the capacity for byte read/write? | 00:06 |
| somlo | there's various declarations of intent to clean that up (e.g., make 32-bit the default instead of 8, tinker with the endianness of how larger-than-8bit CSRs would be stored, etc.) | 00:07 |
| somlo | but for now, that's how it works :) | 00:07 |
| tpearson-mobile | because it just seems weird -- only microcontrollers and some legacy (really *really* legacy) CPUs like x86 have that functionality | 00:07 |
| tpearson-mobile | OK | 00:07 |
| tpearson-mobile | (in fact I don't even know if modern x86 still does byte read or if these days it does a 32 bit or higher read discarding the extra bits behind the scenes | 00:08 |
| awordnot | I don't think anything in LiteX does native 8-bit CSR reads. As far as I can see all CSR accesses go through a Wishbone bridge with a 32-bit width | 00:09 |
| somlo | the wishobone and axi bus protocols support byte strobes, so an 8-bit access would be a 32 or 64 bit access with all but one bytes strobed out | 00:09 |
| tpearson-mobile | OK, so it is just as bad / weird as I thought :) | 00:09 |
| tpearson-mobile | oh well | 00:09 |
| tpearson-mobile | at least it can be overriden | 00:09 |
| tpearson-mobile | *overridden | 00:09 |
| somlo | the CSR bus did not historically support a strobe, there's another plan in the works to teach it to deal with strobes, which would probably fix a lot of issues, no idea at what expense in terms of added "gateware" | 00:10 |
| awordnot | is there any reason that CSR needs to be its own bus instead of just exposing the registers to wishbone? maybe resource utilization? | 00:11 |
| somlo | that's a question for _florent_ (I've mostly tried to get how things work in order to use them, don't have the context for how/why they came to be the way they are) | 00:12 |
| awordnot | sure, fair enough | 00:13 |
| mithro | @awordnot - Resource usage | 00:23 |
| mithro | @awordnot Wide buses which run to lots of peripherals inside the FPGA cost a lot of resources | 00:24 |
| awordnot | mithro: hm. But if the CSR data width was set to 32-bit then there wouldn't be that much of a difference? | 00:24 |
| tpearson-mobile | I have a couple of additional questions if you all don'd mind.... :) | 00:41 |
| tpearson-mobile | How are IRQs handled? | 00:41 |
| tpearson-mobile | The peripheral I'm gluing in has an IRQ line that I'd like to tie to a distinct IRQ (don't care which number) on the CPU | 00:41 |
| tpearson-mobile | Other question is what is the absolute simplest way to run a small C program from internal ROM? | 00:42 |
| tpearson-mobile | benh: On the bootloader console for Microwatt, is the CPU running in BE mode? | 00:43 |
| tpearson-mobile | either it's BE or I've got the byte ordering swapped in the 32 bit CSR stuff :) | 00:43 |
| awordnot | the microwatt doesn't support BE at all yet afaik | 00:43 |
| awordnot | it enters at 0x0 with MSR[LE] set | 00:44 |
| tpearson-mobile | hrm, so it seems when I put the CSR into 32 bit mode the bytes are swapped around | 00:44 |
| awordnot | how are you reading the register? using the generated wrapper? | 00:44 |
| tpearson-mobile | no, "mr <address>" | 00:44 |
| awordnot | and the resulting byte dump has the most significant byte first? | 00:45 |
| tpearson-mobile | LSB first....actually, brain cramp! :D | 00:45 |
| awordnot | heh | 00:45 |
| tpearson-mobile | sorry, I got real used to debugging some of the IBM hardware that runs in BE mode | 00:45 |
| tpearson-mobile | I think we're good | 00:46 |
| awordnot | happens to all of us :) | 00:46 |
| tpearson-mobile | rubber duck debugging FTW... ;) | 00:46 |
| tpearson-mobile | (most of which is restating the "problem" in a way that makes one actually think for a sec) | 00:46 |
| awordnot | as for running custom bare-metal C code, this is a good template: https://github.com/litex-hub/fpga_101/tree/master/lab004/firmware | 00:46 |
| tpb | Title: fpga_101/lab004/firmware at master · litex-hub/fpga_101 · GitHub (at github.com) | 00:46 |
| tpearson-mobile | thanks | 00:47 |
| tpearson-mobile | IRQs then are the only other question | 00:47 |
| awordnot | that unfortunately I'm not sure about | 00:47 |
| tpearson-mobile | I've heard Microwatt may not have IRQ support, but regardless there has to be a way to at least expose them to the Wishbone bus | 00:47 |
| tpearson-mobile | (and on that topic, I've heard there is a potential for the interrupt controller to be XIVE compatible -- that would be really nice) | 00:48 |
| tpearson-mobile | benh: ^^ | 00:48 |
| awordnot | it looks like interrupts are done by using the CSR EventManager: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/csr_eventmanager.py | 00:49 |
| tpb | Title: litex/csr_eventmanager.py at master · enjoy-digital/litex · GitHub (at github.com) | 00:49 |
| awordnot | you can see how the UART core uses it: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L203 | 00:51 |
| tpb | Title: litex/uart.py at master · enjoy-digital/litex · GitHub (at github.com) | 00:51 |
| tpearson-mobile | awordnot: hrm. if my Verilog module has an IRQ line (it could be either level or edge triggered, I don't care), how would I use that then | 01:00 |
| tpearson-mobile | ? | 01:00 |
| awordnot | tpearson-mobile: so you'd create an EventManager submodule, then add the appropriate EventSource for the type of triggering you want. Then you just pass the source's .trigger property to your verilog to use | 01:02 |
| tpearson-mobile | hmmm, OK. No examples online, right? We're dealing with one unknown already (whether Microwatt even has IRQ support), and without a working example that's adding a second unknown that will make debugging quite "fun" ;) | 01:03 |
| awordnot | other than the UART I linked, I can't find any more minimal examples | 01:04 |
| awordnot | maybe temporarily switch the soc to something that's known to support interrupts (like VexRiscv) to test? | 01:04 |
| tpearson-mobile | I guess for a simple test program that's reasonable (ish), though to be honest I have no idea how RISC-V handles interrupts in the first place. Hence why POWER is the target :) | 01:11 |
| tpearson-mobile | (well, it's a lot more than that, the IRQ bit is just the tip of the iceberg -- we're very much set up to handle POWER systems with near-zero experience with RISC-V | 01:11 |
| awordnot | I believe litex provides a C abstraction layer for that, which should be sufficient for simple tests without having to actually write risc-v specific code | 01:11 |
| futarisIRCcloud | 8-bit CSR stuff is a weird one, but done that was to save on resource usage, sort of makes sense. | 01:11 |
| awordnot | but yeah, I see where you're coming from | 01:11 |
| tpearson-mobile | oh, that'd be useful | 01:12 |
| tpearson-mobile | some kind of IRQ test code? | 01:12 |
| awordnot | tpearson-mobile: see the isr_* functions here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/libbase/uart.c#L105 | 01:13 |
| tpb | Title: litex/uart.c at master · enjoy-digital/litex · GitHub (at github.com) | 01:13 |
| awordnot | that example C project I pasted links against those functions, so you can use them to set up ISRs | 01:14 |
| tpearson-mobile | OK | 01:14 |
| tpearson-mobile | ...thanks! lots to digest | 01:15 |
| awordnot | you're welcome :) | 01:15 |
| tpearson-mobile | benh: am I correct in assuming the IRQ status is "not working" for Microwatt"? | 01:15 |
| futarisIRCcloud | I suspect so. Best to try to get that IRQ stuff working in Renode first... | 01:16 |
| tpearson-mobile | what would be needed to add IRQ support? Is it LiteX-specific or more of a general "the CPU doesn't have support"? | 01:17 |
| benh | tpearson-mobile: we have embryonic irq support | 01:22 |
| benh | we plan to beef it up asap to support liteeth | 01:22 |
| benh | at the moment, level interrupts only, we need to add masking support, the problem is Linux requires on FW to do that on xics | 01:22 |
| benh | we need to either add a "native" backend to linux or add a mini-fw layer | 01:23 |
| tpearson-mobile | benh: I can probably help with at least the firmware bits | 01:23 |
| awordnot | OPAL-microwatt :) | 01:23 |
| tpearson-mobile | I've done work with OPAL / skiboot alrady | 01:23 |
| tpearson-mobile | yeah | 01:23 |
| benh | well, I created OPAL :) | 01:23 |
| tpearson-mobile | ah, right :D | 01:23 |
| tpearson-mobile | my bad | 01:23 |
| benh | it would be easier/faster to put a native backend in linux | 01:23 |
| awordnot | for OPAL, BE support would need to be added too, yeah? | 01:23 |
| benh | also our interrupt controller isn't in LiteX yet, I plan to work on that too | 01:24 |
| benh | awordnot: probably... not hard though | 01:24 |
| awordnot | yeah, I'd imagine so | 01:24 |
| benh | we have the swappers already for the byte-reverse load stores, we need to add them to the icache | 01:24 |
| benh | the problem is the icache has tight timing path and so has the decoder | 01:24 |
| tpearson-mobile | benh: OPAL gets us some other things though, right? | 01:24 |
| benh | depends... | 01:24 |
| tpearson-mobile | IIRC all the power management is through OPAL? | 01:25 |
| tpearson-mobile | i.e. power off / reboot etc.? | 01:25 |
| tpearson-mobile | I don't know if we want to completely lose the abstraction | 01:25 |
| awordnot | don't OPAL power management calls just forward to the BMC though? | 01:25 |
| tpearson-mobile | at the moment, but the whole point is that it could change behind OPAL without the kernel caring | 01:26 |
| awordnot | yeah true - I'm just not sure how closely coupled the API is to the existing implementation | 01:26 |
| tpearson-mobile | regardless, it's a published standard sort of like some of the ACPI calls | 01:27 |
| benh | there is no such thing as power management in microwatt today :-) | 01:27 |
| tpearson-mobile | I dunno -- benh might know more the risks / benefits of Yet Another Interface vs. just extending OPAL | 01:27 |
| benh | oh I don't mind doing a mini-opal or a mini-rtas, been thinking about it | 01:28 |
| tpearson-mobile | personally I see too much interface bloat in POWER already | 01:28 |
| benh | we would need to add BE support or define a LE variant of OPAL | 01:28 |
| benh | bbl | 01:28 |
| tpearson-mobile | sure | 01:28 |
| tpearson-mobile | we have two separate interrupt controllers, OPAL (PowerNV), the older interface before PowerNV | 01:29 |
| tpearson-mobile | I'm not sure adding yet another is good for POWER overall :) | 01:29 |
| awordnot | i wonder if it'd be feasible to add an opal no-op backend to linux (i.e. all OPAL calls just forward to regular kernel function calls) | 01:30 |
| awordnot | not sure how elegant that would be though :P | 01:30 |
| tpearson-mobile | awordnot: well, IIRC OPAL at its core is just a set of functions that can be called by the kernel | 01:33 |
| tpearson-mobile | how about just a set of functions in the OPAL table that basically don't do much? | 01:33 |
| tpearson-mobile | shouldn't be too hard | 01:34 |
| awordnot | i'm not sure about ABI differences and you'd have to disable the endian swap but yeah that's basically what i'm envisioning | 01:34 |
| tpearson-mobile | well, ABI can be worked around, does the kernel itself do the endian swap? | 01:36 |
| tpearson-mobile | regardless it'd be better to just add BE support to Microwatt since it increases compliance in the first place | 01:36 |
| awordnot | i think the kernel itself does the swap, yeah | 01:36 |
| tpearson-mobile | yeah, so extending Microwatt to add BE is probably the best option | 01:37 |
| awordnot | and I agree, BE support needs to be added one way or another eventually | 01:37 |
| tpearson-mobile | benh: when you get back....this nascent support, if all I'm wanting to do is make sure an IRQ I'm asserting from a peripheral has made its way over to Microwatt, is it sufficient (i.e. bare metal test program)? | 01:40 |
| benh | tpearson-mobile: there's two interrupt controllers on ppc64 today (there was 3 but I think we took out openpic) | 01:50 |
| benh | xics and xive | 01:51 |
| benh | there are several interfaces on top of them... | 01:51 |
| benh | we currently implement a mini-xics (though it's somewhat incomplete) | 01:51 |
| benh | xics in linux supports 2 interfaces: via opal FW or via RTAS FW | 01:51 |
| benh | but it would be trivial to add a simple native one to the source controller | 01:51 |
| tpearson-mobile | benh: right, and to be honest it's quite a mess right now for not much of a good reason. I don't want to see yet another interface added, since we're starting to go toward RISC-V style "each SoC acts completely different and needs its own special kernel" territory | 01:52 |
| benh | (we do native for the interrupt presentation, it's for source control that we go through fw) | 01:52 |
| benh | yeah but on the other hand, directly poking at a native ICS is about half a page of code | 01:52 |
| benh | we could do a mini-opal or a mini-rtas though ... the latter would require adding 32-bit support though :-) let's not go there | 01:52 |
| tpearson-mobile | P10 will use OPAL / XICS right? | 01:53 |
| benh | adding BE is not hard provided we can make timing in the icache | 01:53 |
| tpearson-mobile | like P9 does? | 01:53 |
| benh | provided IBM doesn't kill native linux completely | 01:53 |
| benh | openpower doesn't look good at the moment... but I don't have insider info | 01:53 |
| benh | P10 is XIVE like P9 | 01:53 |
| tpearson-mobile | XIVE, OK | 01:53 |
| benh | but XIVE is a much much bigger beastm we are nowhere near supporting something like that in mw | 01:53 |
| benh | xics is a lot simpler | 01:53 |
| tpearson-mobile | makes sense | 01:54 |
| benh | but linux doesn't care which one you have, it's orthogonal to the CPU ISA | 01:54 |
| tpearson-mobile | right | 01:54 |
| tpearson-mobile | I know P9 at least does fall back to XICS somehow | 01:54 |
| benh | not really | 01:54 |
| benh | the hw is just xive | 01:54 |
| tpearson-mobile | ah, OK | 01:54 |
| benh | I just hacked a "XICS-like" interface in OPAL on top of XIVE :-) | 01:54 |
| tpearson-mobile | gotcha | 01:54 |
| benh | bcs it took a long time to get full proper XIVE going, it's ... a beast | 01:54 |
| benh | powerful but complex | 01:55 |
| tpearson-mobile | yeah, I guess the main point is XICS isn't going *anywhere* in the mainline kernel | 01:55 |
| tpearson-mobile | it's kind of the equivalent to the legacy IRQ stuff still in x86 | 01:55 |
| benh | right, but then getting things in mainline isn't hard either :) | 01:55 |
| benh | I think long run supporting opal is the way to go | 01:55 |
| tpearson-mobile | yeah, same | 01:55 |
| benh | so we can use the powernv platform rather than a custom microwatt platform | 01:55 |
| tpearson-mobile | exactly | 01:55 |
| benh | that said there are bigger issues at hand and we are massively out of topic for #litex :-) | 01:56 |
| tpearson-mobile | that was one of the thinks we liked about OpenPOWER/PowerNV | 01:56 |
| tpearson-mobile | ah | 01:56 |
| tpearson-mobile | recommended place to continue discussion? | 01:56 |
| benh | hint: we don't have an FPU or a vector unit :_) | 01:56 |
| benh | openpower slack ? | 01:56 |
| benh | and our toolchain more/less requires them... | 01:56 |
| tpearson-mobile | yeah, so on that topic...there's something in the works to do a major push to fix that stupidity | 01:56 |
| tpearson-mobile | toolchain wise | 01:56 |
| benh | ok | 01:57 |
| benh | I have to go, sunday & sunny, time to get my a** out of the appartment :) | 01:57 |
| tpearson-mobile | basically we all got sloppy with IBM as the only vendor making parts, and it has to be corrected for ... reasons ... not just Raptor desires | 01:57 |
| tpearson-mobile | sure | 01:57 |
| tpearson-mobile | can we set up a time to chat more? | 01:57 |
| tpearson-mobile | I'm CDT here | 01:57 |
| tpearson-mobile | so it's basically 9PM | 01:57 |
| benh | use slack, we can find times or just leave messages for async rpelies | 01:57 |
| tpearson-mobile | OK | 01:58 |
| tpearson-mobile | will ping there | 01:58 |
| tpearson-mobile | thanks! | 01:58 |
| benh | np | 01:58 |
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| ronyrus | hi, is there a standard way to implement a sticky bit, clear on read, clear after write, these king of bits/registers in Litex. | 07:50 |
| ronyrus | I searched a little but didn't find it. | 07:50 |
| futarisIRCcloud | benh: great post on linux-litex mailing list. Hopefully it'll get some discussion going, | 08:07 |
| _florent_ | Hi, i can understand the concerns about the difficulties to use LiteX for people with a hardware background | 08:43 |
| _florent_ | Migen and LiteX have been created by people with hardware background (and not the opposite) and some architecture choices were made to improve productivity to create full systems and still allow efficient resource usage. | 08:43 |
| _florent_ | but' it's indeed possible these choices are making things harder if the hardware designer want to implement things with a different approach, and we still have to improve documentation | 08:45 |
| _florent_ | But both flows (traditional Verilog/VHDL vs Migen/LiteX) have advantages/drawbacks and Migen/LiteX has been used to create complex systems/cores that we still maintain and have allowed to create cores/systems that would not have been possible with Verilog/VHDL or would have a nightmare to do with traditional tools. | 08:49 |
| _florent_ | But for hardware people with a clear view/understanding of how they want things to be implemented, if LiteX approach is not close enough, i would recommend using LiteX only for the integration and/or for reusing core it can provide. | 08:53 |
| _florent_ | I'm personnaly using LiteX for different use cases: create full systems with it (fully in Migen/LiteX), create full systems with part on it full Migen/LiteX and others parts in traditionnal VHDL/Verilog/Vendor IP, create full systems with only VHDL/Verilog cores and where LiteX is only used for integration, or just generate standalone cores (LiteDRAM, LiteEth, LitePCIe) in verilog that will be integrated in a | 08:58 |
| _florent_ | traditional flow, etc... | 08:58 |
| benh | futarisIRCcloud: hopefully .. I haven't heard back yet :-) | 08:59 |
| _florent_ | So we provide one approach to create SoCs (and we indeed have to improve documentation) but we don't force others to use exact same approach :) | 08:59 |
| benh | I'd like to help get Linux upstream support asap :) | 08:59 |
| benh | _florent_: it's been super handy to plug in IP blocks into microwatt standalone and I can see the appear for building SoCs, it's great once you get your head around it | 09:00 |
| benh | _florent_: I personally find it a bit harder for low level hw design but then I'm not a hw designer so .. :-) | 09:00 |
| benh | _florent_: ie, if I want to put together a module with a rather convoluted mix of state machines, combo processes, etc... I think it's just a matter of getting used to it | 09:01 |
| _florent_ | ronyrus: the CSR don't have sticky bit support, but you have we/re signals indicating the CSR has been accessed so can implement the behaviour in your logic | 09:01 |
| benh | _florent_: it would make sense to add write-1-to-clear support | 09:02 |
| benh | it's very useful for a number of things where you want atomicity ... for example clearing event bits or interrupt status bits | 09:02 |
| ronyrus | _florent_ : thanks :) is there an example of logic that does that so I can take a look? | 09:02 |
| benh | mind you, arguably anything requiring performance should be normal MMIOs :-) | 09:02 |
| benh | also very useful for error reporting bits | 09:02 |
| benh | it avoids the races of doing read-modify-write where you can end up losing a newly set bit | 09:03 |
| benh | with W1C (or RC but I prefer W1C) you now you only clear what you've seen and it's race free even in multi-processor environments | 09:03 |
| benh | where 2 CPUs might try to collect the same event | 09:03 |
| zyp | isn't W1C already fairly trivial to implement? | 09:04 |
| _florent_ | ronyrus: i will need to write a bit of code, i could do that a bit later | 09:06 |
| benh | zyp: it is in verilog/vhdl ... I suppose it's in migen too ;-) | 09:08 |
| benh | I was just pointing out that it would be a useful feature to have in the base CSR implementation | 09:08 |
| benh | as an option when creating them | 09:08 |
| benh | it needs to be careful though that the write-clear by host and update by the logic itself are properly atomic | 09:09 |
| zyp | true | 09:09 |
| zyp | and I totally agree on the W1C | 09:09 |
| ronyrus | _florent_ only if you want to. I just thought that maybe in some project or module there is such a code already, so you would point me there. No need to do it especially for me. :-) | 09:12 |
| zyp | ronyrus, something like this? https://paste.jvnv.net/view/Xx8xE | 09:14 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 09:14 |
| benh | _florent_: LiteEthPhyModel ... it seems to be using source/sink pads.. what does it connect to ? | 09:56 |
| benh | ah found it | 09:58 |
| benh | litex/build/sim/core/modules/ethernet/ethernet.c | 09:58 |
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| ronyrus | zyp I'm confused, isn't 'we' is strobed when there is a read from the bus? | 10:16 |
| zyp | hmm, I might have r and w the wrong way around | 10:20 |
| zyp | but the rest should still make sense, right? | 10:20 |
| zyp | corrected: https://paste.jvnv.net/view/4tLK7 | 10:22 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 10:22 |
| ronyrus | I think so | 10:22 |
| ronyrus | but I'm fairly new to the FPGA development, so ... | 10:30 |
| _florent_ | just discovered this: https://www.phoronix.com/scan.php?page=news_item&px=LiteDIP-Open-Source-FPGAs | 10:40 |
| tpb | Title: LiteDIP: Creating Open-Source IP Blocks For Generic Linux Drivers On FPGAs - Phoronix (at www.phoronix.com) | 10:40 |
| _florent_ | https://mupuf.org/blog/2020/06/09/FPGA-why-so-few-drivers/ | 10:41 |
| tpb | Title: FPGA: Why so few open source drivers for open hardware? - mupuf.org (at mupuf.org) | 10:41 |
| futarisIRCcloud | MuPuF: I hope to make good progress on this over my summer vacation, with the target of having a minimal DRM driver working over PCie! | 10:56 |
| ronyrus | so, I wrote something that I thought would work, but it doesn't. | 12:16 |
| ronyrus | https://ctxt.io/2/AADAitY0Eg | 12:16 |
| tpb | Title: Context share whatever you see with others in seconds (at ctxt.io) | 12:16 |
| ronyrus | Added it to a module that inherits from AutoCSR. The 'status' signal is going up, but 'w' stays 0. | 12:17 |
| ronyrus | and 'r' is going up at some point for some reason ... ¯\_(ツ)_/¯ | 12:18 |
| ronyrus | I'm using liteScope to sample the signals. | 12:18 |
| ius | how are offsets supposed to be handled when using litex_server with the crossover uart over pcie? | 12:47 |
| ius | litex_server.py maps my PCIe BAR (where 0x0 actually translates to 0x82000000 on the fpga side) but seems to have no builtin way to specify this offset? the latter makes me think i'm not using it right | 12:49 |
| ius | all reads (eg. by litex_crossover_uart.py) rely on the physical address obtained from csr.csv, so one would expect the server to be responsible for address translation? | 12:51 |
| zyp | ius, doesn't look like either of those have any offset arguments | 15:33 |
| zyp | you could alternatively use wishbone-tool, it expects a --register-offset argument | 15:34 |
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| _florent_ | ius: litex_server is not indeed not doing address translation, we could add it or you would also use wishbone-tool as zyp suggests | 15:37 |
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| ius | right, thanks for confirming - wishbone-tool works indeed (i tried it before, was just confused about the python utils) | 16:37 |
| mithro | awordnot: Yes, there is isn't much difference when you make CSR data-width 32bit -- and actually it is somewhat less about resources and more about route-ability of the resources | 17:42 |
| mithro | _florent_: I disagree with the premise if LiteDIP -- but I'm open to being proved wrong | 17:43 |
| mithro | _florent_: My belief is more about the number of users | 17:43 |
| mithro | futarisIRCcloud: did you see the netv2 PCIe driver? | 17:46 |
| mithro | https://github.com/timvideos/litex-buildenv/wiki/HowTo-HDMI2PCIe-on-NeTV2 | 17:47 |
| tpb | Title: HowTo HDMI2PCIe on NeTV2 · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 17:47 |
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| mithro | _florent_: I moved the LiteX for hardware engineers page to the LiteX wiki - https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers | 18:18 |
| tpb | Title: LiteX for Hardware Engineers · enjoy-digital/litex Wiki · GitHub (at github.com) | 18:18 |
| _florent_ | mithro: i've not yet been able to read the full article from mupuf.org, i'll do it soon, i was just sharing it since saw it. I think the work we are currently doing with Antmicro/gsomlo/benh is going in the right direction and we just need to continue discussing things. | 18:33 |
| _florent_ | mithro: thanks for the LiteX for hardware engineers move, some parts will probably need to be re-phrased/partially rewritten and i will look at this. If you want to keep an original version of the document, you should probably also keep it in LiteX-Buildenv. | 18:40 |
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| tpearson-mobile | anyone know what the license is intended to be on the fpga_101 files? | 19:00 |
| tpearson-mobile | Since lab004 seems to contain the canonical non-Linux firmware example, it'd be important to know if it has to be rewritten to be used (irritating) or if the lack of license was an attempt to indicate public domain / CC0 | 19:00 |
| _florent_ | tpearson-mobile: i just added a BSD 2-Clause License with https://github.com/litex-hub/fpga_101/commit/9e48d00cd93d933e6fb6e4d5a0ff144254d08dae | 19:35 |
| tpb | Title: add LICENSE. · litex-hub/fpga_101@9e48d00 · GitHub (at github.com) | 19:35 |
| tpearson-mobile | thanks! | 19:35 |
| tpearson-mobile | much appreciated | 19:35 |
| _florent_ | mithro: i had a closer look at LiteX-for-Hardware-Engineers, i already read it some time ago but wanted to re-read it. I find it very useful for someone wanting to have a quick overview of LiteX and the tips for a someone with a hardware background, but for me this is more a blog post of bunnie's understanding of LiteX when discovering it in 2018. | 19:52 |
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| _florent_ | mithro: but there are some issues: it's a bit outdated, some things are inexacts or biased by bunnie's background/dislike of Python, some things are covered by others wiki pages and explained a bit differently, etc... | 19:54 |
| tpearson-mobile | yeah, agreed | 19:55 |
| _florent_ | mithro: i'm also not sure i want to modify it because it would denaturate it and remove the original content | 19:55 |
| _florent_ | mithro: so i'm probably going to move it in https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources | 19:56 |
| tpb | Title: Tutorials Resources · enjoy-digital/litex Wiki · GitHub (at github.com) | 19:56 |
| tpearson-mobile | to be honest, the intersection of people that are skilled with Python and are also skilled hardware engineers is very small. | 19:56 |
| tpearson-mobile | whether that changes now, we'll have to see | 19:57 |
| tpearson-mobile | most hardware folks are used to being very close to the metal in software terms | 19:57 |
| tpearson-mobile | Python is about as far away as you can get... | 19:58 |
| tpearson-mobile | it's an interesting dicotomy | 19:58 |
| tpearson-mobile | *dichotomy | 19:58 |
| _florent_ | and add a disclaimer that it was a written from Bunnie in 2018 while discovering LiteX, that it can be useful for others people with hardware background, but i would still recommend the others Wiki pages to really learn LiteX and the original reasoning for the concepts. | 19:59 |
| tpearson-mobile | _florent_: quick question, for basic tutorial / quick start files is there any reason BSD is used instead of something that wouldn't require special notices in binaries and documentation? | 20:08 |
| tpearson-mobile | I ask mainly because it's a bit onerous to require that for the life of a project just to get some Makefile templates. If the idea is making LiteX easy to use, basic templates like that should be under a public domain / CC0 type license IMO | 20:09 |
| tpearson-mobile | there's a natural boundary between the gateware and the software already, and it'd be entirely possible to have the gateware under one license and the firmware under another | 20:11 |
| _florent_ | tpearson-mobile: yes i was also thinking of that while adding the license | 20:11 |
| _florent_ | tpearson-mobile: but in fpga_101, there are also some content i'd like to be with this license (or that is some reused stuff with this license) | 20:12 |
| tpearson-mobile | right, makes sense....it's just that fpga_101 is also a de-facto quick start for firmware (basic templates to get things running) | 20:13 |
| _florent_ | tpearson-mobile: so the idea is just to make it use the same license used by LiteX and the cores | 20:13 |
| tpearson-mobile | any way to split those out? Real world example: as you may know we mostly write GPL code publicly, so we'd probably end up rewriting the Makefile just to make licensing less complex | 20:13 |
| tpearson-mobile | that makes using LiteX harder than it needs to be | 20:13 |
| mithro | tpearson-mobile: BSD licenses are compatible with GPL code? | 20:13 |
| tpearson-mobile | they're compatible, yes, but then you have to get into "this file is this license, that file is that license, this file is a chimera of both licenses, see the Git logs..." | 20:14 |
| tpearson-mobile | and for a hour to rewrite a Makefile that's not something we like to do | 20:14 |
| tpearson-mobile | yet....it's an hour of making LiteX harder to use | 20:14 |
| tpearson-mobile | (hour because the docs are quite bad, and if you can't refer to the example Makefile because it's BSD licensed and you're writing a GPL version...) | 20:14 |
| tpearson-mobile | all I'm saying is that adding licenses, even compatible ones, on basic use templates like this is going to make it harder to use LiteX than it needs to be for very little actual gain I can see | 20:15 |
| mithro | tpearson-mobile: You can take a permissively licensed file and convert it to GPL licensed by making modifications and only releasing the modifications under a GPL license | 20:15 |
| mithro | As long as you continue to have the attribution | 20:16 |
| tpearson-mobile | but with two clause BSD you still have to comply with the BSD requirements -- BSD notices in binary and documentation, specifically | 20:16 |
| tpearson-mobile | so it becomes a chimera | 20:16 |
| mithro | @tpearson-mobile Doesn't GPL have the same notice requirements or am I misremebering? People seem to treat it like it does | 20:17 |
| mithro | The GPL has a "Appropriate Legal Notices" section? | 20:18 |
| tpearson-mobile | I'd need to double check, but I do seem to remember BSD being a bit more stringent on it to the point of having banners in command line programs | 20:18 |
| mithro | tpearson-mobile: Are you GPLv2 or GPLv3 | 20:19 |
| tpearson-mobile | we tend to do GPLv3/AGPL | 20:19 |
| mithro | tpearson-mobile: Releasing under GPL means it will probably never be usable in ASICs | 20:20 |
| tpearson-mobile | Right, we had talked about that before, but this is for the *firmware*, which is on the software side :) | 20:20 |
| mithro | https://en.wikipedia.org/wiki/License_compatibility#/media/File:Floss-license-slide-image.png | 20:20 |
| tpb | Title: License compatibility - Wikipedia (at en.wikipedia.org) | 20:20 |
| tpearson-mobile | not the gateware | 20:20 |
| mithro | I'm only partially paying attention -- working on some other stuff | 20:21 |
| tpearson-mobile | sure, no problem | 20:21 |
| tpearson-mobile | mithro: I think the type of license we're looking for in regards to HDL simply doesn't exist -- basically, one that if you modify the HDL itself you have to contribute those changes back, but you can create internal functionally-identical derivative works in the process of making an ASIC | 20:23 |
| tpearson-mobile | without contributing them back (since then you get into NDA protected stuff at foundries etc.) | 20:24 |
| tpearson-mobile | Outside of certain strategic areas (e.g. OpenPOWER / FSI) where it is in our direct interest to allow proprietary implementations of our work, we tend to want people that want to make a proprietary / internal / locked down version of our stuff, instead of contributing back to the open version, to pay for that | 20:26 |
| tpearson-mobile | but...probably a bit OT here :) | 20:26 |
| tpearson-mobile | _florent_: I'm not entirely sure that the lab004 example is actually BSD compliant -- nowhere in the binary does it actually contain the BSD copyright notice :) | 20:32 |
| mithro | tpearson-mobile: My general thinking is that trying to force people to do things doesn't really work -- it's better to create positive incentives so people *want* to contribute back | 20:32 |
| mithro | _florent_: Lots of people like that LiteX for Hardware Engineers page -- many hardware engineers feel uncomfortable Python and understanding that people like Bunnie also struggle with it helps them understand | 20:33 |
| tpearson-mobile | mithro: I agree on short timescales (years), but I disagree on timescales that are the length of copyright (decades to centuries) | 20:33 |
| tpearson-mobile | the "carrot" only works on the shorter timescales in my experience | 20:33 |
| mithro | @tpearson-mobile: Plus permissive can always be converted to repocical if needed in the future | 20:34 |
| zyp | I prefer BSD licensing my embedded stuff, you don't get any contributions back from the people you turn away by GPL-licensing a project anyway | 20:35 |
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| tpearson-mobile | zyp: It's a bit more nuanced I think than that....at least for larger / more valuable works. For little stuff yes, absolutely, we've rewritten small stuff from scratch without even looking at it to avoid license restrictions. For larger projects though where you're starting to talk man-years or more of development, that GPL requirement absolutely | 20:38 |
| tpearson-mobile | can make people start to think twice about just copying and using in proprietary stuff vs. contributing at least something back. | 20:38 |
| tpearson-mobile | sometimes I've seen it change a new design from 100% proprietary to having a clear boundary inside the design of proprietary vs. GPL, just because it's cheaper to do that than to rewrite the entire thing using internal resources | 20:39 |
| tpearson-mobile | anyway, I think without a license-free Makefile example, we need better documentation on key files like software/include/generated/variables.mak | 20:41 |
| mithro | tpearson-mobile: I'm guessing you spend lots of time talking to Bradley Kuhn :-P | 20:41 |
| _florent_ | tpearson-mobile: i don't want to make your life harder, but also don't want to want to make mine harder, BSD-2 is probably a the best fit for most of the work in fpga_101, but please consider there is no restriction on basic things like Makefile, simple firmware, etc... | 20:41 |
| tpearson-mobile | mithro: Nah :D | 20:42 |
| zyp | tpearson-mobile, also, the BSD license does not require the binary itself to contain the license notice, it's sufficient to put it in the accompanying documentation | 20:42 |
| tpearson-mobile | mithro: we've seen both the best in people (/corps) and the worst in people (/corps) | 20:42 |
| tpearson-mobile | zyp: yes, though for embedded firmware it's not like there's normally a software help package that goes with it, oftentimes it ends up embedded in some Flash chip on a board and that's it | 20:43 |
| tpearson-mobile | granted, we always publish something with those types of products that says "get the source here" but I don't know if that satisfies the BSD requirement. | 20:44 |
| tpearson-mobile | _florent_: thanks, that does make it easier :) | 20:45 |
| tpearson-mobile | just because there's a lot of "magic variables" in the Makefiles that will send people on a wild goose chase for no good reason if they had to assemble it all on their own | 20:45 |
| tpearson-mobile | LiteX-specific magic variables, that is | 20:45 |
| mithro | tpearson-mobile / _florent_: Are these the generated files? We could just put a CC0 license at the top of the generated file output? (Generated files are in a strange position in copyright law)? | 20:47 |
| tpearson-mobile | mithro: one axiom we've taken away from our experience is that without the ability to enforce a stick against someone, they will eventually turn on you, it's just a matter of time. At some point the carrot you're offering simply won't keep their interest, and if you don't have enforcement ability you're in a bad spot. Note this is mostly just due | 20:47 |
| tpearson-mobile | to the (IMO insane) copyright durations in the US -- they're long enough that you could have multiple generations own the copyright to any given work. | 20:47 |
| tpearson-mobile | and the last chain in that generational link could easily be an IP holding company that will apply lawyers as needed to get maximum profit for themselves no matter the cost to anyone or anything else ;) | 20:48 |
| _florent_ | mithro: i agree LiteX for Hardware Engineers page has really interesting value as i was saying, but it does not mean that's the way i would recommend learning LiteX. I also don't want to denaturate it by modifying it, so i just moved it to https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources#litex-for-hardware-engineers with a description/disclaimer and haven't touched the contents | 20:48 |
| tpb | Title: Tutorials Resources · enjoy-digital/litex Wiki · GitHub (at github.com) | 20:48 |
| tpearson-mobile | mithro: I don't think the main file in question (the Makefile) is autogenerated | 20:50 |
| tpearson-mobile | but it was generated by someone that was familiar with the LiteX way of doing thing | 20:50 |
| tpearson-mobile | *thinks | 20:50 |
| tpearson-mobile | *things | 20:50 |
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| tpearson-mobile | there's also a little bit of code in main.c that, while useful, isn't worth dealing with licensing over -- there's tons of public domain examples of how to do things like string scans | 20:51 |
| _florent_ | mithro: no sure the generated files should be CC0: i still like to have a BSD-2 license on a LiteDRAM/LitePCIe standalone generated core | 20:51 |
| mithro | _florent_: I hope the wiki will have more contributors than just you? | 20:51 |
| tpearson-mobile | _florent_: You could always mark the couple of little files that we're talking about here as public domain / CC0 in the headers --that would remove any question :) | 20:52 |
| mithro | Can use SPDX identifiers -- https://spdx.org/licenses/ | 20:53 |
| tpb | Title: SPDX License List | Software Package Data Exchange (SPDX) (at spdx.org) | 20:53 |
| tpearson-mobile | yeah | 20:53 |
| tpearson-mobile | that same relicense then allows those to be used in other works (Wikis, etc.) more easily | 20:53 |
| tpearson-mobile | e.g. if we were to put out some documentation on how to use LiteX for things | 20:53 |
| somlo | _florent_: this: https://pastebin.com/txWRww0U fixes it for me on rocket+litex | 20:55 |
| tpb | Title: [Diff] diff --git a/litex/soc/software/liblitesdcard/spisdcard.c b/litex/soc/software/l - Pastebin.com (at pastebin.com) | 20:55 |
| tpearson-mobile | I completely agree on keeping the more complex stuff under a proper license, it's just these building blocks that are really only useful to accelerate someone else's brand new design that I'm having a bit of a license quibble over | 20:55 |
| somlo | not asking to apply it yet :) | 20:55 |
| somlo | but apparently .data and .rodata end up being classified as .rodata (and writes to it are ignored) | 20:55 |
| somlo | making it all go in .bss apparently leaves global variables still writable | 20:56 |
| tpearson-mobile | (and where by nature there's no boundary to clearly mark where one project starts and another ends -- Makefiles have to be part of the resultant firmware sources, for instance) | 20:56 |
| somlo | still investigating (we should be able to use initialized globals in .data and have them stay r/w, anything else is insanity) | 20:57 |
| somlo | but at least I'm likely to be barking up the right tree, so to speak | 20:57 |
| awordnot | somlo: wow that's a very weird bug | 20:57 |
| somlo | tell me about it, it's been driving me up the wall for the better part of last week :) | 20:58 |
| _florent_ | mithro: there are already others direct contribution than mine in the wiki (from somlo for example), but i'd just like to get my change to describe how i see the project, it's taking time because i'm busy with others thins but it's slowly getting there. Once we have this base it will be easier to have others contributors. | 21:01 |
| somlo | _florent_: I wonder if somehow soc/software/bios/linker.ld holds the answer -- my intuition says that's where I need to look next... | 21:08 |
| somlo | hmmm... `INCLUDE generated/output_format.ld`, `INCLUDE generated/regions.ld` ... | 21:10 |
| somlo | the latter (regions.ld) looks fine... | 21:11 |
| somlo | oooh... in linker.ld, we have both .rodata and .data go in `> rom`, only .bss goes in `> sram` | 21:12 |
| somlo | that might explain a thing or two | 21:12 |
| mithro | _florent_: You mean s/change/chance/ right? | 21:12 |
| somlo | let me try and rebuild with a small edit to linker.ld, see what happens | 21:12 |
| somlo | _florent_: what are the implications of explicitly mapping .data into sram (instead of rom)? I'm no ld ninja, so I have to ask if it's likely the memtest might stomp all over initialized .data values in sram during self-test :) | 21:17 |
| somlo | but really, .data *belongs* in sram, as it's supposed to be modifiable by the program! | 21:17 |
| somlo | nvm, I'm being dumb -- memtest stomps all over DRAM, not sram ! :D | 21:18 |
| zyp | somlo, does .data have different LMA and VMA? | 21:24 |
| tpearson-mobile | mithro: FSI code is now BSD 3-clause: https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/-/commit/7b0ac449ecbdfcebffffb3a9522381b2efae4e06 | 21:24 |
| tpearson-mobile | does that work for you? | 21:25 |
| tpb | Title: Relicense FSI master/slave as BSD 3-clause in addition to AGPL v3 (7b0ac449) · Commits · Raptor Engineering Public Development / lpc-spi-bridge-fpga · GitLab (at gitlab.raptorengineering.com) | 21:25 |
| somlo | zyp: we're talking about the litex bios here, so it's all physical addresses at this point | 21:25 |
| zyp | that's not relevant to my question | 21:25 |
| somlo | ok, then I misunderstood your acronyms | 21:26 |
| zyp | on a MCU with flash, it's typical to put .data's LMA in flash and VMA in ram, since the initial contents will be located in flash and copied to ram during startup | 21:27 |
| mithro | tpearson-mobile: Should do | 21:27 |
| tpearson-mobile | great! | 21:27 |
| zyp | when you have .data going into rom, it sounds like you have a linker script written for such a platform | 21:27 |
| somlo | zyp: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/linker.ld | 21:27 |
| tpb | Title: litex/linker.ld at master · enjoy-digital/litex · GitHub (at github.com) | 21:27 |
| somlo | specifically, https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/linker.ld#L55 | 21:27 |
| tpb | Title: litex/linker.ld at master · enjoy-digital/litex · GitHub (at github.com) | 21:27 |
| somlo | that's wrong, IMHO | 21:27 |
| zyp | yeah, that's wrong | 21:27 |
| tpearson-mobile | mithro: there's a few other strategic OpenPOWER-related areas where I can probably get things relicensed if you need, so if you're interested in other files in that repo let me know | 21:27 |
| somlo | should be "> sram", just like bss | 21:28 |
| zyp | agreed | 21:28 |
| somlo | building now to test, will send PR shortly :) | 21:28 |
| somlo | presuming it works, which I think it should | 21:28 |
| daveshah | I think just putting it in SRAM will break XIP platforms? | 21:29 |
| daveshah | that would need some explicit copy-to-RAM step | 21:29 |
| daveshah | unless they use a different linker script | 21:29 |
| zyp | daveshah, which are you thinking of? | 21:29 |
| somlo | daveshah: not familiar with XIP, but having .data that is really .rodata is a recipe for people wasting north of a week thinking they're losing their damn mind :D | 21:30 |
| daveshah | I think some people are using LiteX with the BIOS executing from SPI flash | 21:30 |
| daveshah | e.g. icebreaker | 21:30 |
| daveshah | oh yeah it definitely needs to be fixed | 21:30 |
| zyp | as long as we're talking about code that gets embedded in the bitstream to initialize the ram blocks, you can place it straight into ram unless you need reset capability | 21:31 |
| zyp | if you need to be able to reset, you need a copy of the initial data as well | 21:31 |
| somlo | but if you're executing from SPI flash, you should make sure there is no .data section | 21:31 |
| zyp | https://cgit.jvnv.net/laks/tree/ld_scripts/arm_flash_ram.ld#n72 <- which in a linker script would look something like this | 21:31 |
| tpb | Title: arm_flash_ram.ld\ld_scripts - laks - Microcontroller support library. (at cgit.jvnv.net) | 21:31 |
| somlo | s/no .data section/nothing in the .data section/ | 21:32 |
| zyp | somlo, the .data section exists for a reason | 21:32 |
| zyp | you'll want to handle it properly, not pretend it doesn't exist :) | 21:33 |
| somlo | zyp: right, but if you know you're running stuff from rom, you also know you can't use it | 21:33 |
| zyp | like I said, on a normal mcu with XIP flash, you put an initial copy in flash, and copy it to ram during startup | 21:33 |
| somlo | and like I said, I'm no ld ninja, so if "running from rom" really means implicitly copying stuff into some memory that becomes available later on, then I'm out of my depth | 21:34 |
| somlo | so anyway, I'll send in my PR, and y'all feel free to make me do revisions if it's wrong :) | 21:35 |
| zyp | I don't have time right now, but I can take a look tomorrow | 21:35 |
| zyp | I assume the startup code already has a part that zero-fills .bss? | 21:35 |
| zyp | copying .data from flash to ram goes right next to that | 21:36 |
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| somlo | ok, so then that would be an *additional* patch for XIP platforms, orthogonal to placing .data in sram in linker.ld | 21:37 |
| zyp | I wouldn't call it orthogonal | 21:38 |
| zyp | you'll want something like «> sram AT > rom» in the linker script, along with enough symbols for the startup code to know where to find the data and where to put it | 21:39 |
| zyp | instead of a plain «> sram» | 21:39 |
| somlo | now that I think about it, plain "> sram" probably won't even work, since the startup code won't be there to populate it anyway | 21:40 |
| zyp | unless it's prepopulated in the initial blockram contents | 21:41 |
| zyp | but either way it won't be after a soft reset | 21:41 |
| zyp | which cpu are you working on? | 21:42 |
| somlo | rocket (64-bit) | 21:42 |
| zyp | hmm, I'm getting lost in the repos, where did crt0.S go? | 21:43 |
| somlo | litex/soc/cores/cpu/rocket/crt0.S | 21:44 |
| somlo | there's a bss_init loop | 21:44 |
| somlo | there isn't a "populate data" code block :) | 21:45 |
| zyp | right | 21:45 |
| somlo | so I am starting to comprehend what you're saying, it will be there after pushing the bitstream, but won't get reset to the proper initial values on a soft reset | 21:45 |
| zyp | yes | 21:45 |
| somlo | so really I need two versions of .data, one in rom (to use as a source for memcpy-ing to the second one, in ram) | 21:46 |
| zyp | so you should probably treat everything like a mcu with xip flash, both for .data and .bss initialization | 21:46 |
| zyp | https://cgit.jvnv.net/laks/tree/startup/entry.cpp#n20 <- here's how I do it (along with the linker script I linked earlier) | 21:47 |
| tpb | Title: entry.cpp\startup - laks - Microcontroller support library. (at cgit.jvnv.net) | 21:47 |
| somlo | and somehow expressing this stuff with the appropriate magic incantation in the .ld file, and adding the block of code to do the memcpy on reset | 21:47 |
| somlo | and probably on all CPUs, not just rocket, because it's wrong everywhere right now, even if on some targets it might happen to work by "accident" :) | 21:48 |
| mithro | somlo: The XIP verse copy to ram options should be cleaned up | 21:48 |
| mithro | somlo: https://github.com/enjoy-digital/litex/issues/145 | 21:49 |
| somlo | I'll file an RFC PR and start the conversation, but I'm not equipped to handle a cross-ISA overhaul of everything :) | 21:49 |
| zyp | https://paste.jvnv.net/view/M8Sow <- here's a newer version of that linker script, LOADADDR() makes everything clearer | 21:49 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 21:50 |
| zyp | personally I prefer doing as little as possible in assembly to keep it portable, but that relies on the compiler not attempting to access .data or .bss | 21:51 |
| zyp | before it has initialized them | 21:52 |
| zyp | I wrote this for cortex-m, but I've ran it on vexriscv as well :) | 21:53 |
| somlo | anyway, my dirty-hack attempt at `s/> rom/> sram/` didn't work, the bios hangs after printing the LiteX logo; so I filed issue https://github.com/enjoy-digital/litex/issues/566 | 22:05 |
| tpb | Title: bios: `.data` section placed in rom, wrongly ends up acting like `.rodata` · Issue #566 · enjoy-digital/litex · GitHub (at github.com) | 22:05 |
| zyp | somlo, can you try this? https://paste.jvnv.net/view/tQGMs | 22:17 |
| tpb | Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net) | 22:17 |
| mithro | At some point I would like to write up my theories about how you should use the CSR objects | 22:28 |
| mithro | daveshah: Yes, on the ice40 boards and the spartan 6 lx9 boards the BIOS is stored on SPI flash and XIP rather than inside a ROM | 22:29 |
| zyp | hmm | 22:29 |
| mithro | somlo / zyp: See above too | 22:29 |
| zyp | mithro, just looked at #145 | 22:30 |
| mithro | They don't have enough block RAM to waste it on the ROM | 22:30 |
| zyp | the picorv32/crt0 looks wrong too | 22:30 |
| mithro | zyp: I think we definitely need to add testing for this | 22:30 |
| zyp | it assumes .data is located right after .rodata, which the current linker script doesn't guarantee in any form | 22:31 |
| zyp | and either way, it doesn't really matter whether the BIOS is using XIP SPI flash or block ram configured as a rom, .data can't be located in either since it needs to be writable | 22:32 |
| zyp | the only case in which .data doesn't need to be copied by crt0 is when it's already loaded to ram prior to execution, which would be the case if there's either a loader before this, or if it's using block ram that's initialized by the fpga bitstream itself | 22:35 |
| zyp | but in the latter case, the block ram contents would be modified the first time it runs and therefore potentially invalid after a cpu reset without reloading the fpga | 22:35 |
| somlo | zyp: building now with your suggested patch, let's see what happens... | 22:37 |
| zyp | I also haven't looked at the code that is initializing the block ram, but I'd bet that it currently only initializes the rom block, which is why simply changing to «> sram» didn't work at all | 22:38 |
| zyp | in other words, I'd argue that the #ifdef EXECUTE_IN_PLACE conditional is unnecessary, and that .data should _always_ be copied | 22:40 |
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| zyp | because there's only the special case of a cpu that doesn't need to support reset that doesn't need it to be copied, and that case is currently not supported either way | 22:41 |
| zyp | I guess the only reason it haven't been a bigger problem before is simply because there isn't a lot of code in the BIOS and most of it doesn't write to .data at all | 22:42 |
| somlo | not too many globals, and if any, they're probably .bss not .data | 22:43 |
| zyp | yeah, or they might be in .data but only read | 22:44 |
| somlo | which is why this was such a WTF... whaddaya mean, I'm writing to the damn thing, and it stays unchanged :) | 22:44 |
| zyp | fixing and testing every crt0 sounds fun :p | 22:45 |
| somlo | CPUs (ISAs) should each have a maintainer :) | 22:46 |
| somlo | zyp: that still hangs after the LiteX ascii-art logo and "BIOS built on <timestamp>" | 22:54 |
| zyp | oh, hmm | 22:55 |
| zyp | can I have a copy of the elf and the csr.csv? | 22:55 |
| futarisIRCcloud | mithro: Yep. I've seen the HDMI2PCIe driver. | 22:58 |
| somlo | zyp: http://mirror.ini.cmu.edu/bios.tgz | 23:00 |
| zyp | hmm, at a glance the elf seems to have sane section headers | 23:03 |
| zyp | do you have debugger access to it when it's running? you could set a breakpoint on main and check whether there's matching content at 0x10008600 and 0x11000000 | 23:07 |
| somlo | zyp: no debugger, but I could add some print statements right around where the logo is being printed, presumably before .data is ever accessed... | 23:09 |
| mithro | somlo: Does Rocket have JTAG at all? | 23:09 |
| mithro | somlo: It would be pretty easy to do something like wishbone-tool does for VexRSICV | 23:10 |
| somlo | it probably does, but I'd have to invest a few hours in getting to the bottom of all that :) | 23:10 |
| zyp | this could probably be tested just as well on vexriscv | 23:10 |
| mithro | somlo: Recommend putting it on the todo list near the top | 23:10 |
| zyp | except the copying loop would have to be 32-bit instead :) | 23:11 |
| zyp | somlo, how big is your bios.bin? | 23:12 |
| futarisIRCcloud | https://groupgets.com/manufacturers/getlab/products/kimchi-micro - OSHW i.MX8M based board with a mPCIe slot. | 23:12 |
| tpb | Title: kimχ micro by GetLab | GroupGets (at groupgets.com) | 23:12 |
| somlo | 35k according to `ls` | 23:13 |
| zyp | 35080? | 23:13 |
| somlo | nvm, that was bios.bin; bios.elf is 381920 bytes | 23:14 |
| zyp | I asked about bios.bin :) | 23:14 |
| somlo | oh | 23:14 |
| somlo | 35084 | 23:14 |
| zyp | okay, that sounds sane | 23:14 |
| zyp | judging by the elf, there's 35080 bytes of stuff to go in the .bin, the last 4 is probably just for alignment or something | 23:15 |
| somlo | weird, 35080 divides evenly by 8, 35084 doesn't :) | 23:16 |
| somlo | unless the .bin has 4 bytes worth of some kind of magic file header or something | 23:17 |
| zyp | shouldn't | 23:17 |
| somlo | interesting, right after the last line that prints, there's a call to `crcbios();`... | 23:20 |
| somlo | hmmm... | 23:20 |
| zyp | ah | 23:20 |
| zyp | we probably broke something it assumes :) | 23:20 |
| somlo | that, or crcbios actually uses one or more global variables :) | 23:20 |
| somlo | looking... | 23:21 |
| somlo | https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/helpers.c#L54 | 23:22 |
| tpb | Title: litex/helpers.c at master · enjoy-digital/litex · GitHub (at github.com) | 23:22 |
| zyp | yeah, already found it | 23:22 |
| zyp | and yes, we did | 23:22 |
| zyp | it's trying to do a crc over everything from _ftext to _edata and _edata is now in a different memory region :) | 23:23 |
| zyp | maybe it's not hanging, just busy calculating the crc | 23:23 |
| somlo | well, I could just comment out the call to crcbios for now | 23:23 |
| somlo | rather than worry about fixing it for the purpose of this test | 23:24 |
| zyp | hmm, it's only 16 megabytes between the regions, more likely it's stuck than slow | 23:24 |
| zyp | probably faults once it runs past the end of the rom region | 23:25 |
| somlo | I'm rebuilding with it commented out, should have a verdict in 20-ish minutes or so | 23:25 |
| mithro | somlo: We should get bios patching working -- https://github.com/SymbiFlow/prjxray-bram-patch | 23:25 |
| tpb | Title: GitHub - SymbiFlow/prjxray-bram-patch: Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams. (at github.com) | 23:25 |
| somlo | if it works, it's worth figuring out how to fix it | 23:25 |
| zyp | yeah | 23:25 |
| zyp | I can look more at this tomorrow, should have been in bed an hour ago :) | 23:26 |
| somlo | _florent_ showed me a way to have lxterm push just the bios.bin to a board without rebuilding the whole gateware | 23:26 |
| somlo | didn't work for me right off the bat, so I'd have to invest another hour or two getting to the bottom of *that* :) | 23:27 |
| zyp | anyway, I guess crcbios() is easy to fix | 23:27 |
| zyp | currently it's going off _edata, which is end of .data VMA | 23:27 |
| zyp | changing that to LMA is probably all there's to it | 23:28 |
| zyp | could add a new symbol or do (_rdata + _edata - _fdata) | 23:28 |
| zyp | oh, and the extra four bytes you've got is the CRC checksum :) | 23:29 |
| somlo | heh | 23:29 |
| somlo | zyp: looking at linker.ld, there's an `_erodata` symbol, but then there's a `.commmands` section which I'm unfamiliar with, inbetween .rodata and .data | 23:31 |
| zyp | I assume the .commands is some magic to build an array of commands for the bios shell | 23:32 |
| zyp | you can consider it another .rodata section | 23:32 |
| somlo | so add an `_ecmds = .;` and s/_edata/_ecmds/ in the expected_crc value? | 23:33 |
| zyp | no | 23:34 |
| somlo | figures :) | 23:34 |
| zyp | you want end of .data LMA | 23:34 |
| zyp | which IIRC is easiest to get by doing LOADADDR() + LENGTH() | 23:35 |
| zyp | or maybe it was SIZE() | 23:35 |
| zyp | something like that :) | 23:35 |
| somlo | LENGTH() of what? | 23:35 |
| zyp | anyway, I'll go to bed now and then I'll check the backlog tomorrow to see how your test went, and then I'll update my patch to also fix the crcbios() | 23:36 |
| somlo | ok, sounds good | 23:36 |
| zyp | night :) | 23:36 |
| somlo | back at you, and thanks! | 23:36 |
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