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| sajattack[m] | does migen have an equivalent to verilog's thing where you can assign something multiple times and the last one will take precedence? | 00:07 |
|---|---|---|
| awygle | yes | 00:17 |
| awygle | er, sorry. thought i was in #nmigen and autocompleted an "n" there. no idea about migen lol | 00:18 |
| sajattack[m] | ok well I hope it does | 00:18 |
| sajattack[m] | lol | 00:18 |
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| john_k[m] | It does | 02:24 |
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| dkozel | Hi _florent_ You offered a few weeks to give some guidance on getting my Aller PCIe board up and running with LiteX, could use that help now | 15:33 |
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| dkozel | Board is in and seems to be detected, LiteX and everything else is up to date, and I've built the demo image | 15:33 |
| dkozel | buut... ha, not sure if I even can program it over PCIe or if I need to get the JTAG interface up. | 15:34 |
| _florent_ | dkozel: hi, sure i can try to help | 15:34 |
| _florent_ | so the board is detected with lspci? | 15:34 |
| dkozel | yes | 15:34 |
| _florent_ | ok | 15:34 |
| dkozel | 03:00.0 Memory controller: Xilinx Corporation Device 7024 | 15:35 |
| _florent_ | i'm going to look at the Aller target just to see what it does and what you can test | 15:35 |
| _florent_ | have you already programmed it with the LiteX design or is it the default configuration? | 15:39 |
| dkozel | Default config | 15:40 |
| dkozel | I don't know how to program it (short of the JTAG adapter, which I don't have yet) | 15:40 |
| dkozel | Reading app notes makes it sound like it could/should be possible | 15:41 |
| _florent_ | ah ok, i'm not well aware of what is already loaded to the board | 15:41 |
| _florent_ | i would recommend using using/having a JTAG cable | 15:41 |
| dkozel | Yeah, I've ordered one from Digilent, not sure what their shipping is like at the moment | 15:42 |
| dkozel | bit of an oversight | 15:42 |
| _florent_ | ok | 15:42 |
| dkozel | I'll ping Numato and see if they have a suggestion, otherwise catch you back here in a few weeks | 15:43 |
| _florent_ | i think that would be useful spend 20-30 minutes setting up a design for you based on https://github.com/enjoy-digital/netv2 | 15:43 |
| tpb | Title: GitHub - enjoy-digital/netv2: NeTV2 SoC based on LiteX (at github.com) | 15:43 |
| _florent_ | i'll take the time to do it in the next days | 15:44 |
| _florent_ | please ping me when you know how to reprogram your board and i'll help you getting LitePCIe working | 15:45 |
| dkozel | Thanks. What's useful about that netv2 based design? | 15:45 |
| _florent_ | That's just that i know i tested/updated it recently and the software is included | 15:48 |
| dkozel | Ok, sounds great. I'll let you know when I have more pieces here. Thanks | 15:48 |
| dkozel | My core interest is DMAing data over PCIe to one or more blocks hanging of the wishbone bus or similar, then back up to the host. | 15:50 |
| dkozel | If that helps narrow what bits of the design are most relevant | 15:50 |
| _florent_ | ok, i can easily create a design with that | 15:52 |
| dkozel | Many thanks. I'm looking forward to learning more gateware dev. Almost all of what I've done is debugging DSP inside of existing designs. | 15:53 |
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| pdp7 | trying the orangecrab and getting: | 21:41 |
| pdp7 | build_top.sh: line 4: /opt/Diamond/diamond_env: No such file or directory | 21:41 |
| pdp7 | Is Diamond the lattice ide? | 21:41 |
| miek | yup | 21:44 |
| pdp7 | ah ok... i didn't need for the other ECP5 boards | 21:45 |
| somlo | interesting, the default toolchain is "trellis" in the latest litex-boards git version | 21:46 |
| somlo | i.e. yosys/trellis/nextpnr | 21:46 |
| somlo | for orangecrab, specifically https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/orangecrab.py#L125 | 21:47 |
| tpb | Title: litex-boards/orangecrab.py at master · litex-hub/litex-boards · GitHub (at github.com) | 21:47 |
| somlo | pdp7 any chance your litex-boards repo is a few commits behind the latest? | 21:47 |
| somlo | alternatively, try "--gateware-toolchain trellis" | 21:48 |
| pdp7 | ok thanks | 21:53 |
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| gregdavill | Yep, the old default on the orangecrab was diamond, it's now been updated to Trellis. | 22:06 |
| pdp7 | Thanks all. I can build the gateware now | 22:36 |
| rjeschmi | I'm having a tough time with LiteEth and understanding the clocks. They seem to get renamed on me when I make changes. | 22:47 |
| rjeschmi | for a while they were eth_rx and eth_tx | 22:48 |
| rjeschmi | but now they are eth_clocks_tx and eth_clocks_rx | 22:48 |
| rjeschmi | Is this something to do with AutoCSR? Or is there something I'm missing? | 22:48 |
| rjeschmi | which is only a problem when it tried to compile and eventually gets to: ERROR:ConstraintSystem:59 - Constraint <NET "eth_rx_clk" TNM_NET = | 22:56 |
| rjeschmi | "PRDeth_rx_clk";> | 22:56 |
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