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| futarisIRCcloud | https://www.embeddedonlineconference.com/ - May 20, 2020 | 00:53 |
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| tpb | Title: Embedded Online Conference (at www.embeddedonlineconference.com) | 00:54 |
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| futarisIRCcloud | https://twitter.com/pdp7/status/1222582567137947648?s=19 | 08:37 |
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| atommann | _florent_, seems that at this time netboot does not support KC705, is it easy to port other code to KC705? | 09:03 |
| atommann | (my background was microcontroller programming and I am kinda new to FPGA stuff) | 09:03 |
| atommann | It takes relative long time to transfer software to KC705 board. | 09:04 |
| atommann | Ethernet will be much faster than serial port. | 09:04 |
| _florent_ | atommann: it's probably a typo here: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/make.py#L87 | 09:36 |
| tpb | Title: linux-on-litex-vexriscv/make.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 09:36 |
| _florent_ | can you try with kc705.EthernetSoC? | 09:36 |
| sajattack | _florent_: I updated my PR with my work-in-progress code | 09:55 |
| atommann | OK. I try it now. | 09:56 |
| _florent_ | sajattack: ok, it seems fine, are you able to build it? | 09:57 |
| sajattack | no it errors when I run targets/de10nano.py, and there are some spots I'm not happy with | 09:57 |
| sajattack | particularly where I have to concat the io and the sdram_io to get access to it, and the soc args | 09:58 |
| sajattack | https://hastebin.com/raw/eyadexosuj | 10:00 |
| sajattack | that's the error | 10:00 |
| mithro | _florent_: Do you follow the nmigen soc stuff? | 10:01 |
| _florent_ | sajattack: instead of AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io+_mister_sdram_module_io) | 10:03 |
| _florent_ | you can do AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io) | 10:03 |
| _florent_ | and the line after: self.add_extension(_mister_sdram_module_io) | 10:03 |
| sajattack | ok thanks | 10:03 |
| sajattack | I think it's building now | 10:05 |
| _florent_ | :) | 10:05 |
| sajattack | oh I forgot the --with-sdram | 10:06 |
| sajattack | false alarm | 10:06 |
| sajattack | yeah still fmt error | 10:06 |
| mithro | _florent_: You would probably find the pull requests at https://github.com/m-labs/nmigen-soc/pulls interesting | 10:07 |
| tpb | Title: Pull Requests · m-labs/nmigen-soc · GitHub (at github.com) | 10:07 |
| _florent_ | mithro: i'm following a bit the nmigen-soc work yes, things could indeed be probably be improved a lot but it's not possible to have such radical changes for the projects i maintain that are using Migen/LiteX. So i'm also trying to improve LiteX progressively while trying to keep old code compatible or easy to port. One of the next things i want to do is to be able to switch between Migen and nMigen (in compat mode) | 10:26 |
| _florent_ | for the verilog generation and then evaluate nMigen while doing a new core. And then see if LiteX should also switch to real nMigen (non compat). | 10:26 |
| sajattack | any ideas for my error? | 10:54 |
| miek | sajattack / _florent_: it looks like there's a typo in the code https://github.com/enjoy-digital/litex/blob/master/litex/build/altera/quartus.py#L36 - "fmt.r" should be "fmt_r" ? | 10:59 |
| tpb | Title: litex/quartus.py at master · enjoy-digital/litex · GitHub (at github.com) | 10:59 |
| sajattack | thanks | 11:03 |
| sajattack | hmm so I got it compiled and now I'm not getting into the bios | 11:20 |
| sajattack | oh I got it now | 11:22 |
| sajattack | oh dear memtest fails every test | 11:23 |
| _florent_ | miek: thanks for the catch | 11:23 |
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| sajattack | do I have to do something to set up the sdram clock? | 11:29 |
| sajattack | it's a separate section of the _mister_sdram_module_io and I'm not initializing it anywhere afaik | 11:30 |
| daveshah | sajattack: yeah, you probably want to create a phase shifted clock and drive it by that - e.g. https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/de0nano.py#L69 | 11:32 |
| tpb | Title: litex/de0nano.py at master · enjoy-digital/litex · GitHub (at github.com) | 11:32 |
| sajattack | thanks | 11:32 |
| sajattack | sweet it passed now | 11:39 |
| sajattack | so now I have to load OS over sfl? | 11:40 |
| daveshah | yes, if by OS you mean Linux you will need to build linux-on-litex-vexriscv | 11:45 |
| sajattack | ok, in any case, PR should be ready, linux will probably have to wait until I have an ftdi cable :P | 11:46 |
| sajattack | is it normal for linux-on-litex to not give a bios prompt? | 11:52 |
| sajattack | with only gateware loaded | 11:53 |
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| daveshah | There should still be a bios prompt with linux-on-litex, but IIRC it uses a different baudrate | 11:56 |
| daveshah | something like 500000 or 1000000 for faster kernel loads | 11:56 |
| Claude | afaik 1Mbaud | 11:56 |
| sajattack | ah ok | 11:56 |
| daveshah | you can change it here https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L97 | 11:57 |
| tpb | Title: linux-on-litex-vexriscv/soc_linux.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 11:57 |
| sajattack | it's ok, I got it now at 1mbaud | 11:58 |
| Claude | hmm anyone got a hint for me where to look? i have my own ecp5 board with ddr3 mem. i'm using litesdram with a MT41J128M16JT ddr chip which is in the list of drams supported by litedram. the ddr seems to work, the vecx bios memory test doesn't show any errors and i can write and read data in the bios without errors. so far so fine :) but as soon as i use litesdram my fpga and ddr3 chips get quite hot. same board with just | 12:02 |
| Claude | an risc-v blinking around is cool. i think i got the basic ddr3 layout right, because it seems to work. now i supect something in the ODT termination / and or fpga side termination is off. i can almost adjust the temperature of the ddr3 and fpga by changing the fpga side termination value from 50 to 70 to 100 ohms . 50 = hotest , 100 lowest temperature | 12:02 |
| daveshah | A degree of heat is pretty normal tbh | 12:03 |
| daveshah | given those low termination values, the current involved in DDR3 is pretty high | 12:03 |
| Claude | ok so , for example the ecp5 versa ddr3 gets hot too ? with hot i mean almost too hot to touch | 12:04 |
| daveshah | maybe not quite that hot, but certainly a lot warmer than idle | 12:05 |
| Claude | i will take the board on friday at work, then i can look for excessive under/overshot on the ddr3 lines. currently i have build 3 boards and all show the same symptoms | 12:06 |
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| Claude | actually on a cyclone 5 based design with ddr3 all stays very cool. fpga and ddr get lukewarm | 12:07 |
| sajattack | linux soc in 2727 ALMs, love it! smaller than MiSTer framework :) | 12:09 |
| sajattack | 4180 luts | 12:12 |
| atommann | _florent_, that's cool. netboot works for KC705, and it's fast. | 12:22 |
| _florent_ | atommann: it's indeed a bit faster than serialboot :) | 12:34 |
| _florent_ | atommann: how fast is the Linux boot on the KC705? 5-6s? | 12:34 |
| atommann | about 10 seconds. | 12:38 |
| _florent_ | including the netboot? | 12:39 |
| atommann | yes. | 12:40 |
| atommann | Last year one of my friend designed a board which uses Xilinx 7K325T. | 12:46 |
| atommann | Here's a photo https://imagebin.ca/v/5AbgW9SRnTPA | 12:46 |
| atommann | I am working with him trying to make it work with LiteX. | 12:47 |
| _florent_ | Nice board, what is it used for? | 12:48 |
| atommann | Just a dev board. Like students can use it to learn digital electronics etc. | 12:49 |
| _florent_ | You should be able to get support for it by adapting the KC705 target/platform | 12:49 |
| atommann | In the design my friend used a 12MHz single-ended crystal clock instead of a 200MHz differential clock source. | 12:49 |
| atommann | Today he tried to modify the python file according to Arty board but no success. | 12:50 |
| _florent_ | What was the issue? Compilation or not working on hardware? | 12:51 |
| sajattack | what does this assert mean? for framebuffer assert platform.device[:4] == "xc7a" | 12:52 |
| daveshah | I think it's because the HDMI output stuff is Artix-7 only | 12:53 |
| sajattack | darn | 12:53 |
| sajattack | t'would be quite nice to make use of my hdmi port | 12:54 |
| daveshah | You would have to make an equivalent to https://github.com/enjoy-digital/litevideo/blob/master/litevideo/output/hdmi/s7.py | 12:55 |
| tpb | Title: litevideo/s7.py at master · enjoy-digital/litevideo · GitHub (at github.com) | 12:55 |
| sajattack | hmm, that doesn't look impossible, but this is my first migen project | 12:56 |
| atommann | _florent_, I just called him, compilation passed, I guess he is getting there. | 12:57 |
| _florent_ | sajattack: that could be a bit tricky as a first project, but S7HDMIOutClocking generates the pixel clock (with dynamic configuration, but dynamic configuration could be avoided as a first step), and S7HDMIOutEncoderSerializer is doing the 10:1 serialization. | 13:00 |
| _florent_ | i'm not well aware of the Altera primitives, if 10:1 is possible or not | 13:01 |
| sajattack | yeah idk | 13:02 |
| _florent_ | if not, you will need to use Gearbox to do 10:N and then use the primitive to do N:1, but that becomes a bit complicated for a first project | 13:02 |
| _florent_ | sajattack: using VGA with an external extension board would be easier | 13:03 |
| sajattack | yeah | 13:03 |
| sajattack | oh ok | 13:03 |
| sajattack | yeah I have the vga board | 13:03 |
| _florent_ | ok, then adding VGA support to Linux-on-LiteX-Vexriscv could be a good contribution and should not be too complicated :) | 13:07 |
| sajattack | yeah I'm fairly familiar with vga in verilog | 13:08 |
| sajattack | my first project was a vga test pattern from 8bitworkshop and I've done some MiSTer stuff too | 13:11 |
| _florent_ | ok nice | 13:13 |
| sajattack | MiSTer automagically does vga to hdmi haha | 13:13 |
| _florent_ | ah ok, so if you want to add VGA, you need to add define the VGA pads to your platform, similar to https://github.com/timvideos/litex-buildenv/blob/master/platforms/mimasv2.py#L103-L113 | 13:19 |
| tpb | Title: litex-buildenv/mimasv2.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 13:19 |
| _florent_ | then in a first time, comment this: https://github.com/enjoy-digital/litevideo/blob/master/litevideo/output/driver.py#L52 | 13:19 |
| tpb | Title: litevideo/driver.py at master · enjoy-digital/litevideo · GitHub (at github.com) | 13:19 |
| _florent_ | and create a pix clock domain directly in the target CRG | 13:19 |
| mithro | sajattack: There are a lot of tunnables -- you can make it a *lot* smaller than that I believe | 13:20 |
| _florent_ | then remove the xc7a assert and remove the specific timing constraints: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L161-L168 | 13:21 |
| tpb | Title: linux-on-litex-vexriscv/soc_linux.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 13:21 |
| mithro | Claude: _florent_ is doing a lot of work around LiteDRAM at the moment -- I'm sure he would be very interested in information like that | 13:23 |
| _florent_ | Claude: indeed, that's interesting to know. I'm not sure it was that hot on the ECP5 boards i tested, but i could do more tests if needed. Feel free to open an issue on LiteDRAM to discuss that. | 13:27 |
| sajattack | ok I'll try that soon _florent_ | 13:28 |
| sajattack | I'll borrow or buy an ftdi tomorrow | 13:28 |
| Claude | mithro: ok as soon as I'm sure my hardware is okay I will give more feedback | 13:28 |
| Claude | Ok , but first I triple check the hardware:) | 13:29 |
| daveshah | I remember when I was using the TrellisBoard with a weak USB cable, it actually browned out just when Linux started booting. I do suspect increased DDR3 activity was more significant here than anything going on inside the FPGA | 13:33 |
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| daveshah | TrellisBoard just idling is getting warm but not hot, that's the biggest package so might be spreading the heat more. I definitely remember the Versa ECP5 chip getting significantly warmer | 13:36 |
| Claude | Thanks a lot for testing | 13:58 |
| mithro | kgugala: <tumbleweed> mithro: ERROR: [Place 30-640] Place Check : This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 132 of such cell types but only 100 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a | 14:28 |
| mithro | larger device. | 14:28 |
| mithro | kgugala - tumbleweed is trying to work on getting NeTV2 for PCIe going | 14:29 |
| _florent_ | mithro: which design is it? is it https://github.com/enjoy-digital/netv2/? | 14:30 |
| tpb | Title: GitHub - enjoy-digital/netv2: NeTV2 SoC based on LiteX (at github.com) | 14:30 |
| mithro | _florent_: No the one in litex-buildenv | 14:30 |
| mithro | https://github.com/timvideos/litex-buildenv/blob/master/targets/netv2/hdmi2pcie.py I assume... | 14:31 |
| tpb | Title: litex-buildenv/hdmi2pcie.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 14:31 |
| _florent_ | mithro: ah ok, it's indeed a bit tricky to have PCIe + HDMI on the xc7a35t | 14:31 |
| mithro | https://github.com/timvideos/litex-buildenv/blob/master/platforms/netv2.py#L213 | 14:31 |
| tpb | Title: litex-buildenv/netv2.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 14:31 |
| mithro | I actually believe this NeTV2 is a 100T | 14:32 |
| mithro | But I'm unsure how to check given the part is covered by a head sink... | 14:32 |
| mithro | _florent_: Can you use jtag to read which part? | 14:32 |
| _florent_ | mithro: as just discussed with kgugala, i just added optional CSRs to LiteDRAM DMAs, this make it very easy to let the CPU program the DMA and from the user logic, just used the source or sink | 14:32 |
| _florent_ | https://github.com/enjoy-digital/litedram/commit/090620c9d6ef245af7122b39c6f405201e8fe001 | 14:32 |
| tpb | Title: frontend/dma: add optional CSR control · enjoy-digital/litedram@090620c · GitHub (at github.com) | 14:33 |
| _florent_ | used/use | 14:33 |
| _florent_ | mithro: OpenOCD will read the device ID | 14:35 |
| * tumbleweed can try to read that | 14:36 | |
| tumbleweed | _florent_: also: https://github.com/timvideos/litex-buildenv/pull/310 | 14:36 |
| tpb | Title: shadow_base was replaced by base_address by stefanor · Pull Request #310 · timvideos/litex-buildenv · GitHub (at github.com) | 14:36 |
| _florent_ | tumbleweed: https://github.com/enjoy-digital/netv2/blob/master/netv2.py#L171 | 14:39 |
| tpb | Title: netv2/netv2.py at master · enjoy-digital/netv2 · GitHub (at github.com) | 14:39 |
| tumbleweed | Info : JTAG tap: xc7.tap tap/device found: 0x13631093 (mfg: 0x049 (Xilinx), part: 0x3631, ver: 0x1) | 14:41 |
| tumbleweed | _florent_: OK, so no magics needed | 14:42 |
| _florent_ | tumbleweed: that's an xc7a100t: https://github.com/swetland/jtag-mpsse/blob/master/jtag-mpsse.c#L43 | 14:44 |
| tpb | Title: jtag-mpsse/jtag-mpsse.c at master · swetland/jtag-mpsse · GitHub (at github.com) | 14:44 |
| somlo | _florent_: haven't been following the conversation carefully, but +1 to DMA support in LiteDRAM :) | 14:45 |
| _florent_ | somlo: the DMA was already there, but the used was generating the address stream, not this can be controlled by the CPU | 14:46 |
| _florent_ | so for a DMA Reader, the CPU just programs the base address, length, and start the transfer. The source if the DMA will generate the data and the user can just use it. | 14:48 |
| _florent_ | same for a DMA Writer but in the others direction: the CPU programs the transfer and the user provides the data in the DMA sink. | 14:48 |
| _florent_ | others/other | 14:48 |
| somlo | I'll have to sit down and study all the moving parts, but I'd love to have DMA support in the LiteX+Rocket computer (I think LiteETH would/could be much faster that way) | 14:50 |
| _florent_ | somlo: in fact there were already similar features in LiteVideo, but directly integrated in LiteVideo. Here it becomes more generic and usable for others purposes. (for example here we want to use the DMA Reader to read data from the DDR3 and send it to the PCIe DMA and the opposite). | 14:52 |
| _florent_ | somlo: ie the DMA you can see between LiteDRAM and LitePCIe in https://github.com/enjoy-digital/netv2/blob/master/doc/architecture.png | 14:53 |
| tpb | Title: netv2/architecture.png at master · enjoy-digital/netv2 · GitHub (at github.com) | 14:53 |
| mithro | tumbleweed: You should just be able to change the https://github.com/timvideos/litex-buildenv/blob/c27ca257f49e580183222aa2b10623ae6c544553/platforms/netv2.py#L213 to use a 100t? | 15:03 |
| tpb | Title: litex-buildenv/netv2.py at c27ca257f49e580183222aa2b10623ae6c544553 · timvideos/litex-buildenv · GitHub (at github.com) | 15:03 |
| kgugala | mithro: I have it going on 35t | 15:04 |
| tumbleweed | mithro: yeah, trying it | 15:04 |
| mithro | tumbleweed: It's a bit of a distraction, but we should really finish of https://github.com/timvideos/litex-buildenv/pull/311 too... | 15:04 |
| tpb | Title: WIP -- Modernize platforms + target files by mithro · Pull Request #311 · timvideos/litex-buildenv · GitHub (at github.com) | 15:04 |
| kgugala | with DMA capable of moving data between liteDRAM and host RAM via PCIE | 15:05 |
| kgugala | very dirty code is here https://github.com/antmicro/netv2/tree/v4l2 | 15:05 |
| tpb | Title: GitHub - antmicro/netv2 at v4l2 (at github.com) | 15:05 |
| kgugala | this one have V4L2 driver | 15:05 |
| kgugala | *has | 15:06 |
| mithro | Well, I don't think you can use a 35t bitstream on a 100t part anyway? | 15:07 |
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| mithro | hey rohitksingh! | 15:08 |
| mithro | rohitksingh: Would love your eyes looking over https://github.com/timvideos/litex-buildenv/pull/311 | 15:09 |
| tpb | Title: WIP -- Modernize platforms + target files by mithro · Pull Request #311 · timvideos/litex-buildenv · GitHub (at github.com) | 15:09 |
| rohitksingh | mithro: Hi! Sure, let me go through the PR! | 15:09 |
| mithro | tumbleweed: https://github.com/timvideos/litex-buildenv/pull/311/commits/39274117bbd6c55428df5bbaba87477180317122 | 15:30 |
| tpb | Title: WIP -- Modernize platforms + target files by mithro · Pull Request #311 · timvideos/litex-buildenv · GitHub (at github.com) | 15:30 |
| mithro | tumbleweed: That should probably be merged before the modernize one... | 15:30 |
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| mithro | _florent_: Why do you have to provide a `origin` value to add_memory_region *and* something in mem_map? | 21:33 |
| mithro | Oh - this is the `add_mem_region` verse `add_memory_region` :-/ | 21:36 |
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| _florent_ | mithro: yes, i haven't finish validation of add_mem_region, but we should be able to switch to it soon and simplify the targets | 22:18 |
| mithro | _florent_: I have an alternative I'm about to push | 22:20 |
| mithro | _florent_: Your alloc_mem_region doesn't seem to do what I expected.... | 22:31 |
| mithro | _florent_: https://github.com/enjoy-digital/litex/pull/369/files -- this doesn't quite work | 22:36 |
| tpb | Title: WIP: Attempt at doing a better add_memory_region by mithro · Pull Request #369 · enjoy-digital/litex · GitHub (at github.com) | 22:36 |
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| andresfcalderon | Hi, I'm new here ... but I've already begun to see the magic of LiteX | 22:42 |
| andresfcalderon | Currently I'm testing LiteX on an unsupported board (MATRIX Voice), the board has an FPGA XC6SLX9 with 64MBytes of DDR2. The initialization seems fine (Memtest OK) https://imagebin.ca/v/5AeUVHjSE9dD | 22:42 |
| andresfcalderon | I got an error booting: | 22:42 |
| andresfcalderon | [FLTERM] Got unknown reply 'T' from the device, aborting. | 22:42 |
| andresfcalderon | the full boot message: | 22:45 |
| andresfcalderon | --============== Boot ==================--Booting from serial...Press Q or ESC to abort boot completely.sL5DdSMmkekro[FLTERM] Received firmware download request from the device.[FLTERM] Uploading kernel (50356 bytes)...[FLTERM] Got unknown reply 'T' from the device, aborting.[FLTERM] Booting the device.[FLTERM] Got unknown reply 'i' from the | 22:45 |
| andresfcalderon | device, aborting.meoutBooting from flash...Error: Invalid image length 0xffffffffNo boot medium found | 22:45 |
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| mithro | xobs: I don't think the loopback uart is working for me anymore... | 23:21 |
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