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| sajattack | yo | 07:24 |
|---|---|---|
| _florent_ | sajattack: hi | 07:27 |
| sajattack | so how do I get to the bios prompt? | 07:27 |
| _florent_ | when you load your bitstream, you should get the bios prompt | 07:28 |
| sajattack | it's hard to tell because I don't have an ftdi cable, I've got an arduino hooked up reading the uart | 07:28 |
| sajattack | it only seems to echo my characters | 07:29 |
| _florent_ | in the pull request, you are saying that you have echo, but you should also have the LiteX bios prompt | 07:29 |
| sajattack | ok I'll try to check | 07:29 |
| _florent_ | if you send enter, to you get back "litex>" | 07:29 |
| sajattack | is enter the same as \n | 07:30 |
| _florent_ | yes, try both \n and \r | 07:30 |
| sajattack | ok | 07:31 |
| sajattack | just a minute | 07:35 |
| sajattack | doesn't look like it | 07:37 |
| sajattack | I only loaded gateware, not software | 07:37 |
| sajattack | or firmware or w/e | 07:38 |
| sajattack | I'm not getting an echo anymore either | 07:39 |
| sajattack | maybe I'll go back a few commits | 07:47 |
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| sajattack | ok got it | 08:13 |
| sajattack | wiring pebkac | 08:13 |
| sajattack | b'hello\n\rCommand not found\n\r\x1b[92;1mlitex\x1b[0m> ' | 08:13 |
| daveshah | Looks like your terminal isn't a VT100 :) | 08:14 |
| sajattack | it's picocom | 08:15 |
| sajattack | plus circuitpython | 08:15 |
| sajattack | jank hax because no ftdi cable | 08:15 |
| sajattack | https://termbin.com/9mbv | 08:20 |
| sajattack | if it works it works, right? | 08:22 |
| sajattack | let me squash and stuff | 08:22 |
| sajattack | should be good | 08:26 |
| sajattack | can you guys help me get to linux-on-litex next? | 08:27 |
| _florent_ | sajattack: the bios seems indeed to be working, but you setup does not seem that convenient to use :) | 08:32 |
| sajattack | indeed | 08:33 |
| sajattack | I at least converted the bytes to ascii now | 08:33 |
| sajattack | so it's a little better | 08:33 |
| sajattack | maybe I can make it a bit more interactive too | 08:34 |
| _florent_ | to use linux-on-litex-vexrisc, you need a 32MB memory and on the de10 nano, the DDR3 seems connected to the HPS, so not sure that's easy to access to it from the fabric | 08:37 |
| _florent_ | the de10 nano is the board used by Mister, and there are SDRAM extension available that you could use: https://github.com/MiSTer-devel/Main_MiSTer/wiki/SDRAM-Board | 08:37 |
| tpb | Title: SDRAM Board · MiSTer-devel/Main_MiSTer Wiki · GitHub (at github.com) | 08:37 |
| sajattack | yeah I have one of those | 08:38 |
| sajattack | but I didn't think it was right to stick an optional addon board in the board def | 08:39 |
| _florent_ | you could do it the way we did it on the ECP5 Versa when we were using the SDRAM extension: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/official/platforms/versa_ecp5.py#L147-L165 | 08:41 |
| tpb | Title: litex-boards/versa_ecp5.py at master · litex-hub/litex-boards · GitHub (at github.com) | 08:41 |
| _florent_ | https://pbs.twimg.com/media/DrQ7ATbWwAAnlf1.jpg | 08:42 |
| sajattack | just reuse the pins? | 08:44 |
| _florent_ | yes, you could probably find that in the MiSTer project | 08:45 |
| sajattack | ok will do | 08:45 |
| _florent_ | then you will need to see if the SDRAM module is already defined in LiteDRAM: https://github.com/enjoy-digital/litedram/blob/master/litedram/modules.py#L126-L221 | 08:46 |
| tpb | Title: litedram/modules.py at master · enjoy-digital/litedram · GitHub (at github.com) | 08:46 |
| _florent_ | if not, we could add it | 08:47 |
| sajattack | kk, just doing some circuitpython coding for the last few minutes to have more of an interactive prompt | 08:47 |
| sajattack | much better https://termbin.com/z3mo | 08:48 |
| _florent_ | for the target with the SDRAM integrated, you could look at the de0nano.py: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/official/targets/de0nano.py | 08:48 |
| tpb | Title: litex-boards/de0nano.py at master · litex-hub/litex-boards · GitHub (at github.com) | 08:48 |
| sajattack | the sdram chips on mister are usually alliance or winbond | 08:49 |
| sajattack | I have winbond | 08:49 |
| sajattack | but they're compatible with eachother I think | 08:49 |
| _florent_ | yes probably, but what's the part number? | 08:50 |
| sajattack | let me check | 08:50 |
| sajattack | Alliance Memory | 08:50 |
| sajattack | AS4C16M16SA-6TCN or Winbond W9825G6KH-6 | 08:50 |
| sajattack | for 32mb | 08:50 |
| sajattack | they have 128mb boards too | 08:50 |
| _florent_ | ok, so it's already there: https://github.com/enjoy-digital/litedram/blob/master/litedram/modules.py#L172 | 08:52 |
| tpb | Title: litedram/modules.py at master · enjoy-digital/litedram · GitHub (at github.com) | 08:52 |
| sajattack | yay | 08:52 |
| sajattack | oh shit I think I typed this in backwards because quartus | 09:01 |
| sajattack | so how does this work if they don't have the sdram module? | 09:12 |
| sajattack | I'm looking at versa_ecp5 and you're using SoCSDRAM | 09:12 |
| sajattack | _florent_: ^ | 09:20 |
| sajattack | I guess I add a flag like you do with ethernet | 09:27 |
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| sajattack | anyone there? | 10:25 |
| acathla | hi sajattack | 10:26 |
| sajattack | if I push some weird WIP code can you take a look at it and tell me how to do it properly? | 10:27 |
| sajattack | I'm getting this error and also I'm committing some python/migen crimes migen.fhdl.module.FinalizeError: CPU needs "rom" to be defined as memory or linker region | 10:28 |
| acathla | sajattack, you probably need to define a rom region in your new flash definition | 10:31 |
| sajattack | what flash definition? | 10:32 |
| acathla | ah, you were talking only about sdram, I didn't backlog enough | 10:32 |
| acathla | anyway, your SoC need to have a rom region where you put your bios/bootloader/code to boot to, even if it's in SDRAM. | 10:34 |
| acathla | I guess, i'm learning too... | 10:34 |
| sajattack | where do I define that? | 10:35 |
| sajattack | I checked existing boards platform and target files and didn't see anything with "rom" other than "from" in imports | 10:35 |
| sajattack | maybe I'll just try running linux-with-litex as the builder now | 10:35 |
| sajattack | that doesn't work for another reason | 10:40 |
| acathla | I'm only using small FPGAs yet, without big SDRAM so it's a bit different. Here is the example I'm using : https://github.com/kekiefer/tinyfpga-litex/blob/master/tinyfpga_litex.py | 10:43 |
| tpb | Title: tinyfpga-litex/tinyfpga_litex.py at master · kekiefer/tinyfpga-litex · GitHub (at github.com) | 10:43 |
| sajattack | it looks like that's a step up from where I'm working | 10:44 |
| sajattack | I'm working on a board def | 10:44 |
| acathla | But the concept is sadly to read the source with very few comments in it and to try to understnd how it works, until the docs grow... | 10:44 |
| sajattack | yeah | 10:44 |
| sajattack | oh I think I figured it out | 10:48 |
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| sajattack | new problem lol | 10:58 |
| sajattack | NameError: name 'fmt' is not defined | 10:59 |
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| _florent_ | sajattack: sorry i was away, i can have a look if you share your current platform/target files | 11:26 |
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| somlo | xobs: https://pastebin.com/DA1KWiyk (on top of the current "common.h") | 14:35 |
| tpb | Title: [Diff] diff --git a/litex/soc/software/include/hw/common.h b/litex/soc/software/include - Pastebin.com (at pastebin.com) | 14:35 |
| somlo | xobs: then, restore generated/csr.h to use csr_readl() and csr_writel() with shifts | 14:35 |
| somlo | would that work for you? | 14:35 |
| xobs | somlo: I think it would, yes. Thank you! | 14:36 |
| somlo | cool, i'll cook something up for export.py to do that, then... | 14:37 |
| somlo | xobs: just saw your last reply on github, so question re. naming convention: stick with readl/writel (as in, "long")? Or rather go with csr_read_sub[reg]() and csr_write_sub[reg]() instead? These are after all subregister accessors, not full-CSR ones... :) | 14:42 |
| xobs | Sure, you can do csr_x_sub(). | 14:50 |
| xobs | I just followed the Linux convention. I tend to think of CSRs as being 8-bit registers with contents spread across multiple fields, but I'm not sure anyone else does that. | 14:50 |
| xobs | Comes from working with odd-sized peripherals. Like the i.MX6, which had an 8-bit PWM IP core taken straight from a Coldfire. | 14:51 |
| xobs | So `csr_readl()` and `csr_writel()` made sense to me. But I definitely see the confusion, so for this particular instance `csr_x_sub()` could work nicely! | 14:51 |
| somlo | I'm used to MMIO registers of 32 and 64 bits, so my instinct is to encapsulate the scatter/gather "striping" of the underlying 8-bit limitation as much as possible :) | 14:53 |
| somlo | particularly since LiteX now supports 32bit subregisters, and might support 64bits with a bit more cleanup... | 14:54 |
| somlo | ok, so csr_x_sub() it is, then -- thanks for your patience :) | 14:55 |
| xobs | I think I'll be moving to 32-bit CSRs, because it makes the software simpler and doesn't impact performance too much. It makes no difference with Fomu, and seems fine with Betrusted, too. | 14:59 |
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| somlo | xobs, _florent_: https://github.com/enjoy-digital/litex/pull/366 | 16:03 |
| tpb | Title: software, integration/export: (re-)expose CSR subregister accessors by gsomlo · Pull Request #366 · enjoy-digital/litex · GitHub (at github.com) | 16:03 |
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| sajattack | _florent_: shared | 22:01 |
| sajattack | the TODOs and the fmt error are what I'm struggling with | 22:03 |
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| futarisIRCcloud | https://twitter.com/chisel_lang/status/1222598277268267008?s=19 | 23:01 |
| futarisIRCcloud | CCC = Chisel Community Conference ? | 23:04 |
| sajattack | how do I load a risc-v program to SoCCore? | 23:20 |
| sajattack | sfl? | 23:22 |
| sajattack | this I guess https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_term.py | 23:26 |
| tpb | Title: litex/litex_term.py at master · enjoy-digital/litex · GitHub (at github.com) | 23:26 |
| sajattack | I really need proper ftdi lol | 23:27 |
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