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| keesj | I was wondering about https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/arty.py#L112 | 13:34 |
|---|---|---|
| tpb | Title: litex/arty.py at master · enjoy-digital/litex · GitHub (at github.com) | 13:34 |
| keesj | there dqs_p and dqs_n and clk_p and clk_n are used | 13:34 |
| keesj | the clk_p/n are a differential pair (why are they not defined a "subsignal" | 13:35 |
| keesj | and dqs_p and dqs_n are.. different pairs of differential signals. | 13:35 |
| keesj | on the ddr3 chips I am looking at they are called LDSQ and UDLS (lower an upper byte data strobe) | 13:36 |
| keesj | is there a reason for those names e.g. dqs_p and dqs_n | 13:37 |
| keesj | ? | 13:48 |
| futarisIRCcloud | _florent_: A question from hudson (spispy developer) regarding LiteDRAM: | 13:56 |
| futarisIRCcloud | I need to look into it. Do you know how many cycles it takes to deliver a read? Most of the DRAM implementations I saw had fairly deep pipelines for their arbitrators and interfaces, which made them unsuitable for spispy. Others had hardcoded refresh logic that wasn't easily circumventable, or logic that closed pages too quickly for repeated reads. | 13:56 |
| _florent_ | keesj: sorry, i'm not sure to understand the question | 14:03 |
| _florent_ | https://www.irccloud.com/pastebin/SMoUEU82/ | 14:04 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:04 |
| _florent_ | here the first p/n pair is P(N2)/N(N1) | 14:04 |
| keesj | _florent_: I am wondering about the name. I don't understand why it is called dqs_p | 14:06 |
| _florent_ | futarisIRCcloud: i would need to know the DRAM configuration to provides latency cycles and the requirement for spispy but it should be possible to use LiteDRAM (with eventual minor tweaks) | 14:10 |
| _florent_ | keesj: dqs is commonly used for the data strobe signals | 14:11 |
| keesj | futarisIRCcloud: I think that hudson explained that for spi the data is expected to be retured the next clock cycle just after the address is sent. DDR itself (the sate machine) takes quite a few cycles (bank select) and such. This is I think where the times gets spent. I don't really know about the performance of the bus itself | 14:16 |
| keesj | _florent_: and any idea why _p ? | 14:18 |
| _florent_ | keesj: but i also remember seeing somewhere that they were knowing the address access pattern and were using that to improve latency (pre-opening rows for example) | 14:20 |
| _florent_ | keesj: _p = positive / _n = negative | 14:20 |
| keesj | right but in this case dqs_p is not positive. it is a denominator for the upper data strobe line (for the upper 8 bits) | 14:49 |
| daveshah | ? | 14:49 |
| daveshah | each dqs is usually a differential pair | 14:49 |
| daveshah | N2 would be lower DQS positive and U2 upper DQS positive | 14:50 |
| keesj | thanks I understand it now! the dqs_p contains a list of the positive parts and if there would be 4 lanes it would contain 4 items... In the orange crab https://github.com/gregdavill/OrangeCrab the lines are caled UDQS (differential UDQS+ and UDQS-) and LDQS (differential LDQS+ and LDQS-) so the dqs_p wound become "DQSL+ UDSQ+" | 14:54 |
| tpb | Title: GitHub - gregdavill/OrangeCrab: ECP5 breakout board in a feather physical format (at github.com) | 14:54 |
| keesj | minus the typo | 14:55 |
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