| *** tpb has joined #litex | 00:00 | |
| *** rohitksingh has joined #litex | 00:35 | |
| *** CarlFK has quit IRC | 01:22 | |
| *** CarlFK has joined #litex | 01:38 | |
| *** freemint has quit IRC | 01:52 | |
| *** freemint has joined #litex | 01:54 | |
| *** freemint has quit IRC | 02:05 | |
| *** freemint has joined #litex | 02:06 | |
| *** nrossi has joined #litex | 02:16 | |
| *** freemint has quit IRC | 03:42 | |
| *** freemint has joined #litex | 03:42 | |
| *** freeemint has joined #litex | 03:43 | |
| *** freemint has quit IRC | 03:46 | |
| *** CarlFK has quit IRC | 04:44 | |
| *** rohitksingh has quit IRC | 04:59 | |
| *** CarlFK has joined #litex | 05:19 | |
| *** freeemint has quit IRC | 05:29 | |
| *** freeemint has joined #litex | 05:38 | |
| *** freeemint has quit IRC | 05:43 | |
| *** freeemint has joined #litex | 05:47 | |
| *** freeemint has quit IRC | 05:52 | |
| *** CarlFK has quit IRC | 06:09 | |
| _florent_ | acathla: for CSR access, you can have a look at https://github.com/enjoy-digital/litex/blob/master/test/test_csr.py | 06:10 |
|---|---|---|
| tpb | Title: litex/test_csr.py at master · enjoy-digital/litex · GitHub (at github.com) | 06:10 |
| _florent_ | for Wishbone access, you can have a look at: https://github.com/enjoy-digital/litex/blob/master/test/test_hyperbus.py (dut.bus.write/dut.bus.read) | 06:11 |
| tpb | Title: litex/test_hyperbus.py at master · enjoy-digital/litex · GitHub (at github.com) | 06:11 |
| *** rohitksingh has joined #litex | 06:11 | |
| *** CarlFK has joined #litex | 06:15 | |
| *** rohitksingh has quit IRC | 06:21 | |
| *** rohitksingh has joined #litex | 06:35 | |
| *** rohitksingh has quit IRC | 06:58 | |
| *** CarlFK has quit IRC | 08:10 | |
| *** freeemint has joined #litex | 08:23 | |
| *** shenki has quit IRC | 08:24 | |
| *** spacekookie has quit IRC | 08:24 | |
| *** RaYmAn has quit IRC | 08:24 | |
| *** bonzibuddy has quit IRC | 08:24 | |
| *** kbeckmann has quit IRC | 08:24 | |
| *** shenki has joined #litex | 08:25 | |
| *** bonzibuddy has joined #litex | 08:25 | |
| *** spacekookie has joined #litex | 08:25 | |
| *** RaYmAn has joined #litex | 08:25 | |
| *** kbeckmann has joined #litex | 08:25 | |
| *** freeemint has quit IRC | 08:27 | |
| *** freeemint has joined #litex | 10:01 | |
| *** freeemint has quit IRC | 10:05 | |
| *** freeemint has joined #litex | 11:19 | |
| *** freeemint has quit IRC | 11:24 | |
| *** freeemint has joined #litex | 11:34 | |
| *** freeemint has quit IRC | 11:39 | |
| *** freeemint has joined #litex | 12:21 | |
| *** freeemint has quit IRC | 12:25 | |
| *** freeemint has joined #litex | 12:28 | |
| *** freeemint has quit IRC | 12:32 | |
| *** freeemint has joined #litex | 12:39 | |
| *** freeemint has quit IRC | 12:41 | |
| *** freeemint has joined #litex | 12:41 | |
| *** freeemint has quit IRC | 12:56 | |
| *** freeemint has joined #litex | 12:56 | |
| *** freeemint has quit IRC | 13:25 | |
| *** key2 has quit IRC | 14:04 | |
| *** key2 has joined #litex | 14:10 | |
| *** key2 has quit IRC | 14:14 | |
| *** key2 has joined #litex | 14:20 | |
| acathla | Thank you _florent_. But how did you know the code in uart.py was working? Didn't you already have a testbench for it? | 14:26 |
| _florent_ | acathla: we had a simulation, but i probably removed it while reorganizing the code, i'll try to add one back in the test directory | 14:30 |
| acathla | Ok. I'm a bit lost here. I don't know at what level I should simulate things | 14:39 |
| *** m4ssi has joined #litex | 16:17 | |
| *** CarlFK has joined #litex | 16:28 | |
| *** m4ssi has quit IRC | 16:38 | |
| _florent_ | acathla: sorry i was away, i can give you more informations if you tell me what kind of things you want to simulate and what you want to check | 17:06 |
| acathla | I'm reusing the uart code but with manchester encoding to communicate with infrared | 17:07 |
| acathla | TS4231PHYTX and TS4231PHYRX mostly | 17:08 |
| acathla | oops | 17:08 |
| acathla | I renamed them. class RS232PHYRX(Module): and TX | 17:09 |
| acathla | I don't know what that do : self.source = stream.Endpoint([("data", 8)]) and how to force my Hello world to TX module | 17:09 |
| acathla | Ah, source is for RX, how do I read it? And TX is sink, how do I write to it, from my testbench? | 17:13 |
| acathla | Oh, may be "from litex.soc.interconnect.stream_sim import *" | 17:16 |
| acathla | Hum. no. I give up for today. | 17:35 |
| somlo | daveshah: with latest yosys & nextpnr (as of today, no reverts or other patches), my 256bit wide axi litex-rocket works on the trellisboard, if I dial down Fmax to 60MHz | 19:11 |
| somlo | so it's not a bug per se, rather a diminished ability to find a solution that passes ecp5's actual timing needs | 19:12 |
| _florent_ | acathla: you can look at test_gearbox to understand how to send data to a sink and receive data from a source: | 19:50 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/test/test_gearbox.py#L12 | 19:50 |
| tpb | Title: litex/test_gearbox.py at master · enjoy-digital/litex · GitHub (at github.com) | 19:50 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/test/test_gearbox.py#L25 | 19:50 |
| tpb | Title: litex/test_gearbox.py at master · enjoy-digital/litex · GitHub (at github.com) | 19:50 |
| *** bunnie[m] has joined #litex | 20:09 | |
| *** nrossi has quit IRC | 21:07 | |
| *** rohitksingh has joined #litex | 23:05 | |
| *** CarlFK has quit IRC | 23:43 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!