Tuesday, 2019-12-03

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acathlaIf I want to make a testbench for litex/soc/cores/uart.py, how do I do that? Since it's made to work on a wishbone bus18:20
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davidc__acathla: Use bus.write / bus.read to simulate wishbone bus cycles?18:40
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acathladavidc__, okay, thank you19:47
acathlaIs there an example somewhere?19:48
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davidc__acathla: I think there are examples in litex itself20:43
davidc__(just grep it for "\.write"20:43
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