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| keesj | https://github.com/gregdavill/litex-hyperram/blob/master/hyperbus.py | 08:52 |
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| tpb | Title: litex-hyperram/hyperbus.py at master · gregdavill/litex-hyperram · GitHub (at github.com) | 08:52 |
| keesj | Provides a standard HyperRAM core that works at 1:1 system clock speeds | 08:52 |
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| somlo | _florent_: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/partner/targets/trellisboard.py#L157 should probably get the same treatment versa_ecp5 got in commit d91458c (litex-boards) | 17:58 |
| tpb | Title: litex-boards/trellisboard.py at master · litex-hub/litex-boards · GitHub (at github.com) | 17:58 |
| _florent_ | somlo: indeed, thanks. I'll do that | 17:59 |
| somlo | _florent_: I think that was my mistake originally (sorry about that), so thank you for cleaning up after me :) | 18:11 |
| _florent_ | somlo: no problem, that's difficult to think about all cases when adding features | 18:12 |
| _florent_ | somlo: i just did a quick fix but will try to improve it | 18:13 |
| somlo | I'm still somewhat amazed that I never had to install and use Diamond (so I have a bit of a blind spot when it comes to that)... | 18:16 |
| somlo | _florent_: on an unrelated topic, I'm trying to write a universal "LiteX CSR bus" driver for Linux -- something that knows how to write 8, 16, 32, 64, and 128 bit registers from CPU to hardware preserving the right bit order from MSB to LSB, regardless of cpu endianness, 32 or 64bit alignment, and chunk-size(csr-data-width) | 18:21 |
| somlo | for that, I want to test and double-check my assumptions using the simulator -- is there something there already where I can set up a dummy CSR that simply prints out the value it contains from the perspective of the "hardware" ? | 18:22 |
| somlo | so I can actually test if what I'm writing ends up what the hardware thinks it is receiving, and again when I'm reading a register back into the CPU? | 18:23 |
| somlo | I'll dig around and figure something out, but if there's a one-liner you can point me at for inspiration, that'd make the process MUCH faster :) | 18:24 |
| _florent_ | somlo: sure, you can just use Display with Verilator that is very useful since very similar to a hardware printf | 18:29 |
| _florent_ | somlo: for example: https://github.com/enjoy-digital/usb3_pipe/blob/master/sim.py#L185 | 18:29 |
| tpb | Title: usb3_pipe/sim.py at master · enjoy-digital/usb3_pipe · GitHub (at github.com) | 18:29 |
| somlo | ooh, thanks! (I think you showed this to me once before when I was trying to debug Rocket, back a while ago -- sorry for being thick and not remembering it :) | 18:30 |
| somlo | I think I'll just create a bunch of ctrl_scratch like registers of various widths, and tinker with them from the bios prompt with mr and mw :) | 18:31 |
| _florent_ | the ctrl scratch register was there for this purpose (be sure for that the software was able to access the CSR correctly), if you think this is not enough we could change/improve it | 18:37 |
| somlo | I don't expect anything worth upstreaming into LiteX, just me trying to confirm to myself that I understand how things are scattered/gathered across the register "slices", depending on data-width... I'm usually wrong when I try to guess without testing :) | 18:40 |
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| kc8apf | _florent_: I see you added a method to add timing constraints for S7PCIEPHY | 20:10 |
| kc8apf | That resolves the no_clocks issues. Need to see what my timing report looks like now | 20:11 |
| _florent_ | kc8apf: yes i was apply these timing constraints in the others designs but it was missing in the example design | 20:28 |
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| somlo | Any suggestions to what'd be the more "mature" Big-Endian CPU option to test with (mor1kx vs. lm32)? | 21:40 |
| mithro | somlo: ppcbe? | 22:52 |
| mithro | somlo: Or do you mean in LiteX? | 22:52 |
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