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| mithro | _florent_: Could you give me access to https://github.com/enjoy-digital/minerva-verilog/ ? | 16:42 |
|---|---|---|
| tpb | Title: GitHub - enjoy-digital/minerva-verilog (at github.com) | 16:42 |
| _florent_ | mithro: done, but with https://github.com/enjoy-digital/litex/commit/ab8af28213c5d744e6749b76452f5053feadcf58 we no longer need it | 16:50 |
| tpb | Title: cpu/minerva: elaborate from nmigen sources during build, enable hardw… · enjoy-digital/litex@ab8af28 · GitHub (at github.com) | 16:50 |
| mithro | _florent_: still needed until I update litex-buildenv | 16:52 |
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| mithro | _florent_: https://docs.google.com/spreadsheets/d/1XTHfdYXuvwoYdPXm4M6qDA0D2fZCPy220-9q6qZpTw4/edit#gid=1131619550 | 17:27 |
| tpb | Title: LiteX BuildEnv Support - Google Sheets (at docs.google.com) | 17:27 |
| somlo | PSA: Rocket currently hates yosis: https://github.com/chipsalliance/rocket-chip/issues/2168 | 17:31 |
| tpb | Title: commit #f31e21b5b breaks yosys synthesis · Issue #2168 · chipsalliance/rocket-chip · GitHub (at github.com) | 17:31 |
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| mithro | somlo: Yosys :-P | 18:06 |
| somlo | mithro: sorry, didn't mean no disrespect (I'm just not good at spelling in real time) :D | 18:10 |
| somlo | at least I got it right in #riscv, apparently :) | 18:11 |
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| mithro | _florent_: Could we move rocket-litex-verilog to litex-hub? | 18:20 |
| _florent_ | yes | 18:24 |
| _florent_ | mithro: we could also move minerva-verilog/vexriscv-verilog to litex-hub | 18:26 |
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| mithro | _florent_: Where did get_memory_regions() go? https://github.com/enjoy-digital/litex/issues/290 | 18:53 |
| tpb | Title: Where did soc.get_memory_regions() go? · Issue #290 · enjoy-digital/litex · GitHub (at github.com) | 18:53 |
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| mithro | _florent_: Now I need to figure out how to fix | 19:04 |
| mithro | ValueError: Memory region conflict between spiflash and rom | 19:04 |
| mithro | _florent_: I think I want "add_linker_region" ? | 19:05 |
| _florent_ | mithro: you need to use type="cached+linker" when adding memory region | 20:03 |
| _florent_ | https://github.com/enjoy-digital/litex/pull/285#issuecomment-547973662 | 20:09 |
| tpb | Title: [RFC] Linker region concept by mateusz-holenko · Pull Request #285 · enjoy-digital/litex · GitHub (at github.com) | 20:09 |
| mithro | Looks like the CSR region moved? | 20:16 |
| mithro | ValueError: cas region (0x60006800-0x60006fff) is not located in an IO region. | 20:16 |
| mithro | Available IO regions: | 20:16 |
| mithro | - 0x80000000-0xffffffff | 20:16 |
| _florent_ | mithro: where is the code generating this error? | 20:31 |
| mithro | https://github.com/timvideos/litex-buildenv/blob/96ab220b0f60e3d509ca0a66dcfb81676ef294d9/targets/arty/base.py#L105-L127 | 20:32 |
| tpb | Title: litex-buildenv/base.py at 96ab220b0f60e3d509ca0a66dcfb81676ef294d9 · timvideos/litex-buildenv · GitHub (at github.com) | 20:32 |
| _florent_ | ok, we no longer have shadow_base, so you need to make sure your CSR is in a io region (ie not cached) | 20:35 |
| _florent_ | so you can change https://github.com/timvideos/litex-buildenv/blob/96ab220b0f60e3d509ca0a66dcfb81676ef294d9/targets/arty/base.py#L120 to use 0xe0000000 | 20:36 |
| tpb | Title: litex-buildenv/base.py at 96ab220b0f60e3d509ca0a66dcfb81676ef294d9 · timvideos/litex-buildenv · GitHub (at github.com) | 20:36 |
| _florent_ | and remove the shadow comments | 20:36 |
| mithro | Why 0xe0000000 rather than 0x80000000 ? | 20:37 |
| _florent_ | you can also use 0x80000000, that's was just to use the same addressing as your previous code | 20:42 |
| somlo | _florent_, mithro: for what it's worth, I've switched rocket over to csr/mmio below 0x80000000, and cached RAM above | 20:43 |
| somlo | so that I can grow the RAM to whatever size the hardware provides, without any MMIO region getting in the way | 20:44 |
| mithro | _florent_: https://github.com/enjoy-digital/litedram/pull/94 | 20:53 |
| tpb | Title: Fix broken LPDDR support. by mithro · Pull Request #94 · enjoy-digital/litedram · GitHub (at github.com) | 20:53 |
| mithro | https://github.com/enjoy-digital/litex/pull/293 | 20:53 |
| tpb | Title: Fix file names for the mor1kx processor. by mithro · Pull Request #293 · enjoy-digital/litex · GitHub (at github.com) | 20:53 |
| somlo | trellisboard running LiteX/Rocket, using the full 1GB RAM: https://imgur.com/a/1aIzzL2 | 21:13 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 21:13 |
| daveshah | Very nice! | 21:15 |
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| somlo | daveshah: there's some "hidden slack" in nextpnr's timing analysis, it's usually rated at 52MHz tops, but feels pretty solid at 65MHz | 21:19 |
| daveshah | Yes, that's because it's based on Diamond's default model | 21:20 |
| somlo | some of the lingering weirdness includes passing memtest on svf push via openocd, but failing upon hitting the reset switch | 21:20 |
| somlo | pushing via openocd gets it to pass again (same bitstream) | 21:20 |
| daveshah | Which itself is worst process, minimum Vcc, 85 degrees C | 21:20 |
| somlo | but the latter is related to litedram, not timing, afaict, for the record... | 21:21 |
| daveshah | Have you tried another board yet? It does seem like something is marginal | 21:21 |
| somlo | not yet, will try that tomorrow | 21:22 |
| daveshah | I seem to remember a minimum frequency for the ECP5 DDRDLL | 21:22 |
| daveshah | that was around the 70MHz ish mark | 21:22 |
| daveshah | This was in my experiments before litedram | 21:22 |
| daveshah | It is possible something misbehaves in a way that varies between boards and chips below this | 21:22 |
| daveshah | Unfortunately I don't think it's actually documented anywhere | 21:23 |
| somlo | so maybe the versa has more slack than the trellisboard, since the former works OK at 55MHz (with rocket, that is), and the latter pretty consistently at 65, both of which are lower than the "official" number you quoted :) | 21:23 |
| daveshah | But a DDRDLL issue would explain why either it works or doesn't after a reset | 21:23 |
| daveshah | A typical "marginal" issue would likely not change after a reset and just be odd errors here or there, including in Linux | 21:24 |
| somlo | ok, so I'll add "unboxing a secontr trellisboard" to my agenda for tomorrow, then maybe adding sdcard support, so I can boot fedora or debian from there similarly to how LowRISC does it | 21:26 |
| somlo | as an alternative to a diskless NFS setup, which might be painful for other reasons... :) | 21:27 |
| mithro | somlo / daveshah: antmicro + kgugala are working on LiteSDCard support for both Linux and testing on hardware | 21:28 |
| mithro | Does the trellisboard have a sd card connector? | 21:28 |
| daveshah | Yes, it does | 21:28 |
| mithro | daveshah: What would we need to do to get antmicro a trellis board? | 21:29 |
| daveshah | I can't really encourage anyone to build more given there is an unknown DDR3 reliability issue | 21:29 |
| daveshah | Along with a few other rev 1.0 niggles | 21:30 |
| daveshah | I don't know if forksand or somlo would be able to part with one of theirs | 21:32 |
| mithro | daveshah: How similar is the versa board? | 21:33 |
| daveshah | mithro: smaller fpga, less ddr, no HDMI, only x1 pcie, less IO | 21:34 |
| daveshah | somlo: FYI, this patch was to get nfs boot working on a previous litex lnux project | 21:34 |
| daveshah | https://github.com/daveshah1/litex-linux-riscv/compare/master...daveshah1:nfs | 21:34 |
| tpb | Title: Comparing master...nfs · daveshah1/litex-linux-riscv · GitHub (at github.com) | 21:34 |
| daveshah | Although fairly slow, it was pretty painless | 21:35 |
| mithro | daveshah: Can you log an issue somewhere for someone to clean that up? | 21:38 |
| daveshah | Yeah, sure | 21:39 |
| mithro | daveshah: I mean -- if you log an issue somewhere with that, I'll see if someone at antmicro has time to clean that up and make it work | 21:39 |
| daveshah | mithro: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/54 | 21:41 |
| tpb | Title: Add support for NFS rootfs · Issue #54 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 21:41 |
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