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| bonzibuddy | hey gurus - im pluggin along, trying to get more utilities in my rootfs, but every time i customize the config the system hangs on 'waiting on /dev/ram0...' | 03:43 |
|---|---|---|
| bonzibuddy | my hypothesis is that im trying to upload an image too big for the mem area? still need to confirm that. hoping someone's worked around this one before | 03:43 |
| bonzibuddy | customize the buildroot config & upload via lxterm*** | 03:46 |
| futarisIRCcloud | bonzibuddy: What's the size of your ramdisk in .config and the image size? | 04:57 |
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| Guest124578 | Hi, | 09:32 |
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| hello_pico | Maybe a silly question : is it possible to make a Vivado project manually which would be similar to what LiteX scripts do ? (I was expecting for a simpier code when looking at the Verilog generated by LiteX) | 10:09 |
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| somlo | _florent_, daveshah: the litedram native port width on the trellisboard is indeed 256, so I'm inclined to bump the hard-coded mem_axi width on Rocket to 256, and downconvert for boards with narrower litedram ports (e.g., ecp5versa at 128, nexys4ddr at 64) but use full unimpeded width where available | 16:36 |
| bonzibuddy | futarisIRCcloud: i'll check that this evening, that's likely the issue | 16:43 |
| somlo | daveshah: trying to build litex+rocket for the trellisboard, and I usually get to 60MHz easily (no need for -nowidelut, plenty of room), but consistently fail to meet the 125MHz for '$glbnet$eth_clocks_rx' (getting in the neighborhood of 115MHz, typically) | 18:50 |
| daveshah | Interesting | 18:51 |
| daveshah | Possibly the larger chip makes placement worse | 18:51 |
| daveshah | or just different Ethernet pin placement or something | 18:51 |
| daveshah | I haven't noticed this with VexRiscv when I've tried previously though | 18:52 |
| somlo | I am now trying with a lower (55MHz) cpu clock, to see if that has some second-order effect on the ethernet timing | 18:54 |
| somlo | but I'm just basically throwing rocks at it :) | 18:54 |
| somlo | if that doesn't immediately make a difference, I'm just going to let it loop | 18:54 |
| somlo | not sure if it's worth trying with the "unmet" ethernet fmax, using --timing-allow-fail | 18:55 |
| daveshah | Yes, definitely | 18:55 |
| daveshah | Another thought is to remove abc9. I think I've seen it reduce Ethernet Fmax in the pat | 18:56 |
| daveshah | *past | 18:56 |
| somlo | ok, forgot about abc9, thanks for that. | 18:58 |
| daveshah | Hmm, looking into this myself and I got 124.63MHz on a first try | 19:14 |
| somlo | yeah, it's all probabilistic... asked for 58MHz, got 62.60 for main, 128.55 for eth... Wish I'd just asked for 60 like earlier :) | 19:14 |
| somlo | I want to get to the good bits, where I use an unhindered point-to-point 256bit axi channel between litedram and the rocket chip :) | 19:16 |
| somlo | find out what that does for my benchmark measurements... | 19:16 |
| somlo | daveshah: any plans to add a trellisboard.cfg to /usr/share/trellis/misc/openocd (in prjtrellis) ? | 19:18 |
| somlo | hmmm... memory initialization failed (https://imgur.com/a/QMsxij4) | 19:22 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 19:22 |
| daveshah | Done, I wasn't expecting anyone else to build one... | 19:22 |
| daveshah | Ah, that's not so good | 19:23 |
| daveshah | The board I have seemed fine, maybe try another board? | 19:23 |
| somlo | so you think this is a hardware error, then | 19:23 |
| daveshah | Probably, could be the litedram change of course | 19:24 |
| daveshah | I'm also not sure if I've ever tested the trellisboard at frequencies other than 75MHz | 19:24 |
| somlo | oh, so when it worked for you it was vexriscv, not rocket? | 19:24 |
| daveshah | Yeah | 19:24 |
| somlo | I should try that before I toss this one in the bin as "bad" :) | 19:24 |
| daveshah | Can you give me the bitstream? I can test it here | 19:24 |
| daveshah | Definitely don't bin it whatever - the FPGA is alright which is what really matters | 19:25 |
| somlo | stand by... | 19:25 |
| somlo | daveshah: mirror.ini.cmu.edu/top.svf | 19:26 |
| somlo | http, that is... | 19:27 |
| daveshah | Works fine on the board you sent me | 19:27 |
| daveshah | https://www.irccloud.com/pastebin/Umb3BfTC/ | 19:27 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 19:27 |
| somlo | well, that makes me happy and sad, at the same time :D | 19:28 |
| somlo | thanks for checking! | 19:28 |
| daveshah | Hang on, hitting reset a couple of times I hit a failure like yours too | 19:29 |
| daveshah | Maybe something is just a bit marginal | 19:29 |
| somlo | maybe the clock is too low... | 19:29 |
| somlo | let me kick it a few times on this end, see what happens | 19:29 |
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| somlo | well, this one fails pretty consistently. Do you have a vexriscv bitstream I could just shove at it? | 19:33 |
| daveshah | https://usercontent.irccloud-cdn.com/file/Z3TLRh6j/top.svf | 19:35 |
| daveshah | This one is pretty old but has always been reliable | 19:35 |
| daveshah | FWIW, there seems to be some hardware variation too. On the other board you sent me, and a board from my own batch; the bitstream you sent seems to work 100% of the time | 19:35 |
| somlo | ha | 19:36 |
| somlo | "memtest ok" \o/ | 19:36 |
| daveshah | note there are two ways to try a reset - reloading the svf or pressing SW2, might be a difference between the two | 19:36 |
| daveshah | Interesting | 19:36 |
| daveshah | Possibly something a bit marginal in the controller then | 19:37 |
| somlo | gets wobbly when the main clock gets too low | 19:37 |
| daveshah | Tweaking the +1 and +2 to either +0 and +1 or +2 and +3 might increase reliability | 19:38 |
| daveshah | https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/ecp5ddrphy.py#L442 | 19:38 |
| tpb | Title: litedram/ecp5ddrphy.py at master · enjoy-digital/litedram · GitHub (at github.com) | 19:38 |
| daveshah | Or, just trying a different board... | 19:39 |
| somlo | I'm not physically close to my stash of alternative boards, so I'll try the hacks first, see what shakes loose... | 19:43 |
| somlo | daveshah: just for a sanity check: my reset switch is the leftmost of the group of four; if I hit the "standalone" one on the left of the board, I have to reload the svf | 19:45 |
| daveshah | Yes, that's right | 19:45 |
| somlo | can't read the labels on the pcb, my glasses are "tuned" for 20-inch focal distance, i.e. my computer monitor :D | 19:46 |
| somlo | it *never* fails at 75MHz with the vexriscv bitstream | 19:47 |
| daveshah | Yeah, I've never had issues with that bitstream or any other 75MHz bitstream on any board | 19:47 |
| daveshah | OTOH, the same PHY works fine at 55MHz or 60MHz on a Versa | 19:48 |
| somlo | yeah, rocket seems happy on a versa anywhere north of 55MHz | 19:52 |
| daveshah | But, different PCB layouts, double chips might mean longer routing and less margin, ... | 19:53 |
| daveshah | Let me just try a new 75MHz vex bitstream to make sure it isn't a regression | 19:54 |
| somlo | ok, in the mean time I'll try getting a proper 60MHz rocket bitstream, maybe more if I turn off abc9... | 19:55 |
| daveshah | New 75MHz bitstream seems fine too | 19:56 |
| daveshah | https://usercontent.irccloud-cdn.com/file/0bUEcrdL/top.svf | 19:57 |
| somlo | seems to pass memtest for me as well (there's a weird delay before I get the "ok" prompt, and "no boot medium found", but it *is* "memtest ok" nonetheless, each time I kick it... | 19:59 |
| daveshah | That's because picorv32 is slow :)? | 19:59 |
| daveshah | I was alarmed by it too at first | 20:00 |
| somlo | ok, so I'll try to figure out how far I can tweak fmax and the litedram cl_sys_latency offsets | 20:00 |
| daveshah | 65MHz seems alright here too, but that might be a bit ambitious for Rocket | 20:01 |
| daveshah | seems to be 60MHz where it fails | 20:01 |
| daveshah | As it seems to either work or not (either a lot of failures or none at all, never just one or two failures), it might be a problem with the startup FSM | 20:04 |
| daveshah | https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/ecp5ddrphy.py#L56 is another magic number (probably to increase) | 20:04 |
| tpb | Title: litedram/ecp5ddrphy.py at master · enjoy-digital/litedram · GitHub (at github.com) | 20:04 |
| somlo | of course, if any of that tweaking actually turns out to help in a reliable way, we'd have to regression test on the versa, to make sure the modifications aren't mutualy exclusive between the two boards... | 20:08 |
| daveshah | Yes, this is very true | 20:08 |
| daveshah | Can you try this bitstream on your board (58MHz, with t=12)? https://usercontent.irccloud-cdn.com/file/vBj3EH7I/top_58M_t12.svf | 20:14 |
| somlo | failed: https://imgur.com/a/IkSYy3V | 20:22 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 20:22 |
| daveshah | Hmm, no idea then | 20:24 |
| somlo | was this with a modified 't' (guessing s/8/12/) in ecp5ddrphy.py line #56 ? | 20:26 |
| somlo | I'll eventually work my way up to trying the offsets on line #442, but I'm hoping I can push fmax a few MHz above 60, into "maybe works most of the time" territory :) | 20:28 |
| daveshah | Yup | 20:28 |
| daveshah | You could try an even higher 't' perhaps, it definitely improved reliability for me | 20:28 |
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| somlo | daveshah: used --timing-allow-fail, requested 65MHz, officially got 57, passed the ethernet clock timing | 21:00 |
| somlo | running it at 65MHz now, booted linux just fine | 21:00 |
| daveshah | Nice | 21:00 |
| somlo | not sure whether *not* using abc9 helped, I'd have to test that a bit more thoroughly (right now I've been haphazardly trying whatever sticks) | 21:01 |
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| somlo | if that turns out to matter, I'll make it an optional build flag rather than a hardcoded thing | 21:01 |
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