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| keesj | Executing booted program at 0xc1000000? | 06:48 |
|---|---|---|
| keesj | should the load address not be the emulator loaded at 0x2000_0000 | 06:48 |
| keesj | the dtb won't... be the one to contain executable code | 06:49 |
| keesj | peraps that the load order is changed based on .. the key order | 06:53 |
| keesj | e.g. self.boot_address = self.mem_regions[list(self.mem_regions.keys())[-1]] needs to be changed to return a list of images to load (and not depend the load order based on a key balue) | 06:54 |
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| keesj | https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_term.py#L137 | 06:55 |
| tpb | Title: litex/litex_term.py at master · enjoy-digital/litex · GitHub (at github.com) | 06:55 |
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| Dolu1 | @daveshah I did some test with increased i$/d$ and it significantly improved the bandwidth, actualy 4KB is i$ and d$ is realy few. In case of you want to try, the max size of for each way is 4 KB. | 07:04 |
| Dolu1 | daveshah : also, i will work on allowing the i$/d$ memory bus to be wider than 32 bits. | 07:05 |
| Dolu1 | I don't know if there is a way in linux to do a ethernet loopback, this would allow to test the bandwidth with all layers excepted the net driver. | 07:06 |
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| keesj | lo | 08:16 |
| _florent_ | hi | 08:16 |
| _florent_ | Dolu: for the improved bandwidth, it's the ethernet bandwidth with your SPI ethernet module? | 08:16 |
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| Dolu1 | _florent_ : Yes, 4*4 KB i$ + 2*x KB d$ doubled the iperf3 results | 10:17 |
| Dolu1 | Also, that's one thing i would like to do, allowing each way to be larger than 4 KB | 10:18 |
| _florent_ | Dolu1: ok thanks | 10:25 |
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| somlo | daveshah: with your ecp5_rocket_versa5g branch rebased on top of yosys #f604aa1, and `synth_ecp5 -abc9 -nowidelut -dsp`, I ran the ecp5versa rocket linux variant builder at 60MHz in a loop | 12:25 |
| somlo | it finally passed timing after 10 hours or so, approximately 20 attempts :) | 12:25 |
| somlo | I'll get a chance to try it out in a few hours, after I make it into the office | 12:25 |
| somlo | got ethernet and tftp working yesterday, with the no-MMU version, so I'm hopeful :) | 12:27 |
| somlo | at 60MHz, like you said | 12:27 |
| daveshah | For test purposes, you can safely ignore a small timing failure so long as the FPGA is <<85°C (there is about 5% of general pessimism in there anyway) | 12:28 |
| daveshah | I think the TFTP code needs a bit of looking at generally though | 12:29 |
| daveshah | Particularly around lost packets and the like | 12:29 |
| somlo | heh, it's the "Unreliable Datagram Protocol" after all :) | 12:30 |
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| _florent_ | daveshah, somlo: yes i need to look at the TFTP issue: https://github.com/enjoy-digital/litex/issues/205 | 13:13 |
| tpb | Title: TFTP transfer bug · Issue #205 · enjoy-digital/litex · GitHub (at github.com) | 13:13 |
| daveshah | _florent_: not sure if this is the same issue, that seems to be when file size is a multiple of blocksize | 13:14 |
| _florent_ | _florent_: ah ok, since it's not easy to reproduce, i'll probably start by looking at the issues with the versa at 50MHz | 13:19 |
| daveshah | It's really weird | 13:27 |
| daveshah | 55MHz seems to work fine (just testing with picorv32 for simplicity) | 13:27 |
| daveshah | at 50MHz not even seeing ARPs in wireshark | 13:27 |
| _florent_ | is there a switch between the board and the computer? If not, wireshark should show the packet even if malformed | 13:38 |
| daveshah | No, I'm on my laptop at the moment so it's just a USB3-Ethernet adapter | 13:40 |
| daveshah | Pretty sure I've seen malformed packets with this setup in the past though | 13:40 |
| daveshah | I do see a blinking light on the adapter side port though, so it's definitely trying to send something | 13:41 |
| _florent_ | ok, i'll look at that while looking at the others issues with TFTP | 13:45 |
| daveshah | OK, on an old laptop with a real ethernet port I see some malformed packets | 14:07 |
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| daveshah | https://usercontent.irccloud-cdn.com/file/9Z6ZFDSh/Screenshot%20from%202019-07-10%2014-58-47.png | 14:11 |
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| sorear | This is the “doesn’t work at 50 Mhz” problem? | 14:27 |
| daveshah | Yes | 14:33 |
| daveshah | I'm thinking it's something that can't keep up, after the CPU | 14:33 |
| daveshah | The CPU clock frequency is unlikely to be an issue, as if a picorv32 at 55MHz can keep up then rocket at 50MHz should certainly be able to | 14:34 |
| daveshah | But a lot of Ethernet stuff seems to be in the fixed 125MHz domain, so the problem is in the middle somewhere | 14:34 |
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| somlo | daveshah: the 60MHz ecp5versa rocket linux variant actually works -- tftp transfer completes, linux boots, busybox prompt, the works | 14:42 |
| daveshah | Very nice! | 14:42 |
| somlo | I'm seeing packets in and out over eth0, but udhcpc can't successfully acquire a lease, for some weird reason | 14:42 |
| somlo | but given that tftp completed, it's likely not the "hardware"... | 14:43 |
| daveshah | I didn't try udhcpc, but I did get a ping to work at least | 14:43 |
| daveshah | manually setting up an ip with ifconfig | 14:43 |
| somlo | so, whatever moral support I can provide to have the ecp5_rocket_versa5g branch upstreamed, and -dsp flag supported, I'm all in | 14:44 |
| somlo | sadly I'm not qualified to actually *review* the patched :) | 14:44 |
| somlo | *patches | 14:44 |
| daveshah | The DSP work is more of a long-term project that needs exhaustive testing | 14:44 |
| daveshah | given the large number of different mapping rules | 14:44 |
| somlo | any time you need me to re-test, happy to do so | 14:44 |
| daveshah | Thanks, will do | 14:45 |
| daveshah | There might be some changes to the nextpnr packer at some point to improve packing density, although I'm not sure if that will hurt routeability too much | 14:45 |
| somlo | daveshah: re. udhcpc, it's definitely not the hardware or software -- I can manually configure an IP, and successfully telnet into 151.101.128.81 port 80 :) | 14:57 |
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| somlo | updated my instructions at http://www.contrib.andrew.cmu.edu/~somlo/BTCP/ with pointers to the patch, and with the binary top.svf file I managed to build overnight, for whomever wants to play but doesn't have the time to spend looping :) | 15:18 |
| tpb | Title: A Trustworthy Free/Libre Linux Capable 64bit RISC-V Computer (at www.contrib.andrew.cmu.edu) | 15:18 |
| somlo | nice to actually have a truly Free option, since that's the narrative I'm pusing :D | 15:18 |
| somlo | *pushing | 15:20 |
| * somlo heads over to the coffee machine | 15:20 | |
| _florent_ | daveshah: for the 50MHz ethernet issue, i would put a litescope analyzer on tx_cdc.sink: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/mac/core.py#L104 | 15:26 |
| tpb | Title: liteeth/core.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 15:26 |
| _florent_ | to see if the packet is valid here | 15:26 |
| _florent_ | and then same analyzer, but on tx_cdc.source running with eth_tx clock domain | 15:26 |
| daveshah | I'm probably not going to get to this until Tuesday now, but I'd be curious what the recommended route to combining litescope with a soc is? I've only ever seen it used on designs without a CPU before? | 16:52 |
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| CarlFK | should this get me a working linux on Arty? https://github.com/enjoy-digital/linux-on-litex-vexriscv-prebuilt | 19:15 |
| tpb | Title: GitHub - litex-hub/linux-on-litex-vexriscv-prebuilt: Prebuilt bitstreams / linux images for litex-on-litex-vexriscv repository (at github.com) | 19:15 |
| CarlFK | Liftoff! and nothing... | 21:58 |
| CarlFK | I'm giving a talk this Sat on "booting linux on fpga" which currently is going to be "sorry, doesn't work." | 21:59 |
| CarlFK | I have Arty, Opsis, Atlys, Fomu and something I'm not sure where it came from | 22:18 |
| CarlFK | Opsis would be a good prop "now it boots hdmi2usb, now it boots linux" | 22:19 |
| CarlFK | woot - built from master, boots on Arty | 22:40 |
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