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CarlFK | juser@cnt5:~/lhub/linux-on-litex-vexriscv$ ./sim.py | 00:24 |
---|---|---|
CarlFK | Compile board device tree... | 00:24 |
CarlFK | sh: 1: dtc: not found | 00:24 |
futarisIRCcloud | sudo apt-get install device-tree-compiler | 00:25 |
CarlFK | futarisIRCcloud: should I enter issues somewhere? | 00:38 |
futarisIRCcloud | Ask _florent_ ... | 00:38 |
futarisIRCcloud | Maybe we just need to update the README.md ... | 00:39 |
CarlFK | run_dut.sh: line 1: obj_dir/Vdut: No such file or directory | 00:40 |
CarlFK | ah.. bet we need build-essentials | 00:40 |
CarlFK | make[1]: g++: Command not found | 00:41 |
futarisIRCcloud | Yep | 00:49 |
CarlFK | [ 0.449490] Unpacking initramfs... | 00:50 |
CarlFK | [ 3.730470] workingset: timestamp_bits=30 max_order=13 bucket_order=0 | 00:50 |
CarlFK | that was way more than 3 seconds :p | 00:50 |
CarlFK | mount: mounting tmpfs on /dev/shm failed: Invalid argument | 00:52 |
CarlFK | is that a problem? | 00:52 |
CarlFK | buildroot login: root - woot! | 00:53 |
CarlFK | the ascii art is all mangled | 00:53 |
CarlFK | cat /proc/cpuinfo | 00:54 |
CarlFK | processor: 0 | 00:54 |
CarlFK | No processor :p | 00:54 |
CarlFK | Vivado wants to install to /tools/Xilinx - do I want that or /opt/Xilinx? | 01:15 |
futarisIRCcloud | You can install there, and symlink, or just install to /opt/Xilinx ... | 01:16 |
mithro | CarlFK: please log bugs on the repo for now | 01:45 |
CarlFK | mithro: k - looged the missing packages | 01:50 |
CarlFK | mithro: is cpuinfo: processor: 0 a bug? | 01:50 |
mithro | Yes | 01:50 |
CarlFK | is arty what I want for: ./make.py --board=arty --build | 02:05 |
futarisIRCcloud | Yes. If it's the board from linux.conf.au 2018. | 02:16 |
CarlFK | https://github.com/litex-hub/linux-on-litex-vexriscv#load-the-fpga-bitstream | 02:22 |
tpb | Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com) | 02:22 |
CarlFK | ./make.py --board=arty --load | 02:22 |
CarlFK | Error: libusb_open() failed with LIBUSB_ERROR_ACCESS | 02:22 |
CarlFK | should I install the udev rules from https://github.com/litex-hub/litex-buildenv-udev ? | 02:23 |
tpb | Title: GitHub - litex-hub/litex-buildenv-udev: udev rules for LiteX BuildEnv supported boards (at github.com) | 02:23 |
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CarlFK | Executing booted program at 0xc1000000 | 03:04 |
CarlFK | --============= Liftoff! ===============-- | 03:04 |
CarlFK | what should happen after that? | 03:04 |
CarlFK | mithro: futarisIRCcloud.. I think it is stuck ^^^ | 03:23 |
mithro | CarlFK: That is when Linux should boot I think? | 03:23 |
mithro | CarlFK: I'm guessing its probably the same issue that xobs ran into with csrs moving.... | 03:24 |
futarisIRCcloud | It should boot. Someone has broken something. | 03:26 |
mithro | futarisIRCcloud: My guess is same change which cause an issue with https://github.com/enjoy-digital/litex/issues/212 | 03:27 |
tpb | Title: Overlapped memory regions fail silently after bitstream generation · Issue #212 · enjoy-digital/litex · GitHub (at github.com) | 03:27 |
mithro | > with the new offset of the csr region, which is at 0x02000000-0x12000000. | 03:27 |
futarisIRCcloud | Probably | 03:29 |
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keesj | I have had the same issue when flashing the stuff (on the arty board) but not when uploading via lxterm. In my case I am already on 0x2000_000 | 05:56 |
keesj | 0 | 05:56 |
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xobs | Are there any examples of projects using SpiFlash()? | 08:50 |
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_florent_ | xobs: probably not published, let me prepare something | 09:08 |
xobs | _florent_: I have something somewhat working, I think I just need to get the "dummy" value right. | 09:09 |
keesj | I found (not migen based) this project quite interesting https://github.com/osresearch/spispy | 09:09 |
tpb | Title: GitHub - osresearch/spispy: An open source SPI flash emulator and monitor (at github.com) | 09:09 |
keesj | where the spi interface is implemented in the FPGA | 09:09 |
_florent_ | xobs: ah sorry, i thought you were speaking of https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi_flash.py#L284 | 09:16 |
tpb | Title: litex/spi_flash.py at master · enjoy-digital/litex · GitHub (at github.com) | 09:16 |
_florent_ | xobs: so if you are using SpiFlashDualQuad/SpiFlashSingle, yes you'll probably have to adjust the dummy parameter | 09:17 |
_florent_ | if you know the content of you Flash, you use mr command of the bios to figure it out | 09:18 |
_florent_ | see: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/15#issuecomment-493203348 | 09:19 |
tpb | Title: Issue booting linux on ArtyA7 · Issue #15 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 09:19 |
_florent_ | keesj: indeed, that's interesting and probably tricky to be able to provide the read data in the amount of time allowed! | 09:20 |
xobs | What is the "dummy" parameter units? It looks like it's the number of dummy clock cycles, minus a few cycles depending on the Wishbone width? | 09:21 |
_florent_ | it's in spi clock cycles, wbone_width is the length of the data transfer | 09:25 |
keesj | of "course" with ddr we might have more time . I just expected the slave to be able to have more slack | 09:25 |
keesj | I tried similar stuff (just tracing) on eMMC and that one starts at 12 Mhz does to 48 but then goes to 200 HS mode(200 Mhz , 8 data lines) that is really getting seriously challenging to emulate I guess | 09:27 |
keesj | in their case they already know what blocks are going to be requested in what order | 09:28 |
_florent_ | not sure ddr would be a lot better since we the important thing here is latency | 09:28 |
_florent_ | if you know what is going to be requested, that' a bit easier indeed :) | 09:29 |
keesj | (they presented a hack in the box amsterdam). pertty nice because for one of the guys it was really his first project | 09:30 |
keesj | https://community.cypress.com/docs/DOC-9250 (there might be some way to configure the read latency) | 09:34 |
tpb | Title: Read Access Latency and Latency Code - KBA219110 | Cypress Developer Community (at community.cypress.com) | 09:34 |
keesj | but .. not if you are trying to attack secure boot | 09:35 |
_florent_ | mithro, futarisIRCcloud: just for info, the mem_map is not changed on linux-on-litex-vexriscv since we are forcing it | 10:41 |
_florent_ | just to be sure, i rebuilt everything for arty, it's working | 10:42 |
_florent_ | maybe the issue is related to a the spiflash and dummy bit configuration: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/15#issuecomment-493203348. | 10:43 |
tpb | Title: Issue booting linux on ArtyA7 · Issue #15 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 10:43 |
futarisIRCcloud | Ok | 10:56 |
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daveshah | somlo: can confirm rocket works on TrellisBoard! https://www.irccloud.com/pastebin/kZ8dEAam/ | 14:59 |
tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:59 |
daveshah | (avoided the most recent patch that limited to 512MB, updated size in device tree and added free to BusyBox) | 15:02 |
_florent_ | daveshah: nice, thanks for the pull request on litex-boards, i'll remove the 512MB limitation soon, main_ram was conflicting with csr on for linux-on-litex-vexriscv, haven't investigated yet | 15:17 |
daveshah | _florent_: this was my hack a while ago https://github.com/daveshah1/linux-on-litex-vexriscv/commit/4bb8cd9a06565b34470dd5fc4b6b07a914dbcf56#diff-1c3a073ba4b12612a2c65941bd2a5842R69 | 15:18 |
tpb | Title: Add TrellisBoard, 1GB hack · daveshah1/linux-on-litex-vexriscv@4bb8cd9 · GitHub (at github.com) | 15:18 |
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daveshah | but before the changes on the litex side | 15:19 |
daveshah | that hack also needed a change to the vexriscv io range | 15:19 |
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_florent_ | thanks yes i'll change the location of the csr | 15:21 |
somlo | daveshah: awesome! | 16:00 |
xobs | It seems like the magic dummy value I'm looking for is "6". | 16:03 |
somlo | I have an "action item" to update to the latest busybox, I should remember to also add "free" to the list of utilities :) | 16:03 |
xobs | Now I just need to figure out why SPI writing isn't functioning correctly. Reading works, erasing works, reading the SPI ID works, but no data actually gets written. I'm wondering if it isn't misaligning the number of clock pulses somehow... | 16:04 |
daveshah | somlo: It would be nice to try a NFS rootfs at some point (I did this to test a bigger buildroot system with the vexriscv stuff) | 16:06 |
daveshah | Probably no good for a distro without a faster Ethernet core though... | 16:07 |
somlo | also, with the way Rocket's external connectivity is wired, it'd be nice to have the AXI port speaking directly to DRAM separated from the CSR/MMIO + bootrom + device buffers wishbone bridge, which whould be connected to the MMIO AXI port on Rocket | 16:10 |
somlo | daveshah: I still haven't had a chance to try ecp5versa placement hacks (now that I showed my bosses it boots, my reward is that I get to write a crap ton of reports :D | 16:14 |
somlo | but what I meant to ask was, did you get the ethernet working on ecp5versa? Even when I leave out the MMU and fit within 45K slices comfortably, it still won;t link up for me | 16:15 |
daveshah | Yes, but you have to use a system clock frequency ≥60MHz | 16:18 |
daveshah | and accept that timing marginally fails | 16:18 |
daveshah | TFTP didn't work for me at 50MHz, not sure why | 16:18 |
somlo | oh, that explains it | 16:18 |
daveshah | I think the LiteX TFTP client could do with some reliability improvements | 16:18 |
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CarlFK | Liftoff still doesn't liftoff | 22:09 |
daveshah | Have you tried serial boot? | 22:10 |
CarlFK | that is all I have tried | 22:11 |
daveshah | What about the simulator? | 22:12 |
CarlFK | that worked yesterday | 22:12 |
daveshah | Might as well double check today | 22:12 |
CarlFK | I'll try now, yeah.. | 22:12 |
daveshah | That should at least confirm your emulator and kernel are built correctly | 22:12 |
CarlFK | its booting | 22:14 |
daveshah | What board is this? | 22:16 |
CarlFK | Arty http://paste.ubuntu.com/p/qJKDXZt8XB/ | 22:17 |
tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 22:17 |
daveshah | Hmm, not sure what's going on | 22:25 |
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