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| CarlFK | mithro: I've been testing the 'same' build - 60 fail jpeg, 6 pass | 04:08 |
|---|---|---|
| mithro | CarlFK: well, that is a good set of samples | 04:09 |
| mithro | CarlFK: is this automated? | 04:09 |
| CarlFK | mithro: the 380's are the fails, the 321 are the pass: http://paste.ubuntu.com/p/yb6W3NbJF6/ | 04:09 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 04:09 |
| CarlFK | yes | 04:09 |
| mithro | CarlFK: That is super helpful. It means when we do fixes we can see if we can get better than 10% success rate... | 04:10 |
| CarlFK | mithro: neat. I loogged the gst test output, but not the build. I'll do that and see if I can find anything useful | 04:12 |
| mithro | CarlFK: yes - being able to compare the successful builds verse the failures is useful | 04:12 |
| mithro | CarlFK: Can you just save the whole build/opsis_hdmi2usb_lm32 directory? | 04:13 |
| CarlFK | mithro: sure | 04:14 |
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| CarlFK | mithro: those 6 builds aren't good after all. - If I run the gst test on the same build enough times, it will pass, but the image is broken: https://veyepar.nextdayvideo.com/static/temp/loopy-1.png | 05:06 |
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| _florent_ | CarlFK: i just re-tested linux-on-litex-vexriscv with prebuilt bistream and image and loading with lxterm and it's working here | 08:10 |
| _florent_ | daveshah: the easiest way to use LiteScope with a SoC is to create a second serial with spare IO pins + USB<-->RS232 dongle, and then just use this serial for the analyzer | 08:12 |
| _florent_ | the rest is similar | 08:12 |
| _florent_ | another way is to create a standalone litescope core like here: https://github.com/enjoy-digital/netv2/tree/master/gateware/litescope | 08:16 |
| tpb | Title: netv2/gateware/litescope at master · enjoy-digital/netv2 · GitHub (at github.com) | 08:16 |
| _florent_ | and then just do an instance in your design | 08:16 |
| keesj | _florent_: did you also happen to try the --flash ? | 08:18 |
| _florent_ | keesj: yes, just tested it, also working, but Arty is mounted with different SPI flashes, if you have trouble it's probably this: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/15#issuecomment-493203348 | 09:41 |
| tpb | Title: Issue booting linux on ArtyA7 · Issue #15 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 09:41 |
| _florent_ | keesj: we need to ease supporting different SPI flashes: https://github.com/enjoy-digital/litex/issues/215 | 09:42 |
| tpb | Title: Improve SpiFlash · Issue #215 · enjoy-digital/litex · GitHub (at github.com) | 09:42 |
| keesj | I see | 10:23 |
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| CarlFK | _florent_: using Arty, prebuilt didn't get past Liftoff, but building from source booted and worked | 13:59 |
| _florent_ | CarlFK: ok thanks, are you using latest prebuilt (i rebuild things a few days ago) | 14:00 |
| _florent_ | ? | 14:00 |
| CarlFK | _florent_: hmm, I think so, but i better double check, which will be in about 2 hours | 14:03 |
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| _florent_ | CarlFK: i just did the test again, being sure to remove all images before copying the prebuilt, and it's working on my setup | 14:13 |
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| CarlFK | _florent_: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/29 where should lxterm be? | 15:13 |
| tpb | Title: readme litex_term.py needs more · Issue #29 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 15:13 |
| CarlFK | I fond it in /home/juser/.local/bin/lxterm - which isn't in my path. | 15:23 |
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| CarlFK | _florent_: fresh install, sim.py worked, Arty stopped at Liftoff | 16:06 |
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| mithro | _florent_: I was thinking the BIOS could just use the SPI bitbanging to set the dummy bits register in the SPI flash to match the FPGA gateware? | 17:38 |
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| CarlFK | mithro: for re-building Opsis-hdmi2usb is there a file I can delete and then run "make image" to just re-run the suspicious part? | 17:56 |
| mithro | CarlFK: not really | 17:57 |
| CarlFK | mithro: does "make clean" do what is needed? | 17:57 |
| mithro | CarlFK: make clean is probably a little aggressive? | 18:00 |
| mithro | CarlFK: mv "build/opsis_hdmi2usb_lm32/" "build/opsis_hdmi2usb_lm32.$(date)/" should work? | 18:01 |
| CarlFK | k | 18:01 |
| CarlFK | mithro: i'm setting up a new box to build hdmi2usb - is this where I should start? https://github.com/timvideos/litex-buildenv/wiki/Bootstrap | 18:15 |
| tpb | Title: Bootstrap · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 18:15 |
| mithro | CarlFK: updated the wiki with instructions on setting the PLATFORM value | 19:08 |
| CarlFK | mithro: k, thanks | 19:09 |
| CarlFK | mithro: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/32 | 19:40 |
| tpb | Title: bootstrap: fxload *NOT* found · Issue #32 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com) | 19:40 |
| _florent_ | mithro: yes if that's possible to configure the dummy value in the SPI flash, that's easier | 20:36 |
| daveshah | I don't think all flashes support this though | 20:38 |
| CarlFK | _florent_: any interest in looking into why my prebuilt on Arty fails? (if I build it works) | 20:57 |
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| CarlFK | can someone point me to a URL to download risk-v? | 22:12 |
| CarlFK | for my talk, as an example of "we really do download a cpu core" | 22:13 |
| sorear | CarlFK: risc-v is not a core, it’s a specification for cores | 22:19 |
| CarlFK | one URL plese :p | 22:19 |
| sorear | download it here: https://github.com/riscv/riscv-isa-manual/releases | 22:20 |
| tpb | Title: Releases · riscv/riscv-isa-manual · GitHub (at github.com) | 22:20 |
| CarlFK | https://github.com/chipsalliance/rocket-chip I think thats one of what I want | 22:25 |
| tpb | Title: GitHub - chipsalliance/rocket-chip: Rocket Chip Generator (at github.com) | 22:25 |
| somlo | CarlFK: you can build LiteX with Rocket as its (64-bit) CPU (--cpu-type rocket [--cpu-variant linux]) | 22:53 |
| CarlFK | somlo: I just finshis my 22 slides - do you have 5-10 min to review them? | 22:54 |
| somlo | but all other CPU cores supported by LiteX are also (versions of) CPUs you can download in source form, probably from github as well :) | 22:54 |
| CarlFK | im not downloading anything and I doubt anyone listening to my talk will either - it is more "here is the state of things" and "come to the hackfest in 2 weeks" | 22:55 |
| somlo | CarlFK: understood, it's just that hardware these days (very much like software) is "something you write in an editor, then compile". True, for hardware, if you make dedicated silicon ASICs, ther's that last stage of the compilation process that takes 6-12 months and costs $1Bn, but *conceptually* that's just an optimization step of the compiler :) | 22:58 |
| * somlo is not a *real* hardware engineer, so to those in this channel who are, please-please don't kick me *too* hard :) | 22:59 | |
| CarlFK | mithro: (and anyone else) mind reviewing my slides? https://veyepar.nextdayvideo.com/static/temp/fpga-clug19.pdf | 23:05 |
| CarlFK | 23:05 | |
| somlo | CarlFK: when I give talks to audiences not familiar with FPGAs, I tell them "it's like an electronic *breadboard* on a chip, and bits from a special memory tell it how to wire itself up" | 23:10 |
| somlo | kinda lame, but works -- feel free to use it :) | 23:10 |
| CarlFK | not bad - not sure my audience (linux users) really know what a bread board is | 23:11 |
| CarlFK | mithro says "it's a little black thing that pretends to be some other little black thing" | 23:12 |
| somlo | I'd hazard a guess that if you show a bunch of linux users the *picture* of a breadboard, they'll recognize it -- may not have the word "breadboard" for it in mind, but they'll know what it's for :) | 23:13 |
| somlo | and yes it can all be open source, with the right FPGA (Lattice ECP5 or ice40, and yosys/icestorm/trellis/nextpnr) | 23:14 |
| somlo | it can even run linux -- there's enjooy-digital/linux-on-litex-vexriscv on github (32bit Linux), and then there's www.contrib.andrew.cmu.edu/~somlo/BTCP (64bit stock linux on Litex & RocketChip, shameless self-promoting plug :) | 23:16 |
| somlo | other than that, it's a pretty decent teaser deck for your hack fest :) | 23:19 |
| CarlFK | your "all" isn't big enough :p | 23:19 |
| CarlFK | or, something I've never understood - Arty has Atrix-35t - do I have to use Vavado? | 23:20 |
| somlo | Arty has a xilinx chip, so (for now, modulo SymbiFlow progress I haven't kept up with) -- yes, you need to use Vivado | 23:22 |
| somlo | Arty, nexys4ddr, and a bunch of other boards are based on the Artix 7 FPGA from Xilinx | 23:23 |
| somlo | OTOH, the Lattice FPGAs (normally programmable with Lattice's proprietary tool called "Diamond") have been reverse engineered almost completely, and one can build complex designs for them (e.g. a fully Linux capable Litex) with 100% open source tools (yosys/trellis/nextpnr) | 23:25 |
| somlo | The other *major* FPGA maker is Altera (owned by Intel, iirc), and their toolchain is called "Quartus" | 23:27 |
| somlo | if you're US based, it's analogous to Lattice being the T-Mobile to Xilinx's Verizon and Altera's AT&T, or something :D | 23:27 |
| somlo | smallest and hacker-friendliest of the bunch | 23:28 |
| mithro | somlo / CarlFK - I normal say "It's an IC that can pretend to be other ICs" | 23:40 |
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