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| _florent__ | Dolu: thanks for the link | 05:37 |
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| _florent__ | Dolu: i think the boot time is directly related to the CPU freq and type of RAM that is used, but yes i should investigate a bit | 05:38 |
| Dolu | _florent__ : Is there a way to get a simulation which include the DDR stuff ? i can then check the wave and what happen on the busses. | 07:25 |
| keesj | perhaps litedram/examples/sim might be a good start _florent__ mentioned it was possible to test using.. xsim | 07:38 |
| _florent__ | Dolu: yes we can simulate with LiteDRAM and a SDRAM model | 08:09 |
| _florent__ | Dolu: but for now the capability to initialize the SDRAM model is missing... | 08:09 |
| _florent__ | so i would need to add it or have a look directly on hardware | 08:10 |
| _florent__ | the boot time of the avalanche board seems really slow compare to the others boards with similar CPU freq/RAM | 08:12 |
| futarisIRCcloud | The avalanche board was with the old vexriscv... | 08:12 |
| _florent__ | but it's using the Microsemi DRAM controller, i haven't tested efficiency/bandwidth with it | 08:12 |
| futarisIRCcloud | I wonder what the boot time is like on a PSRAM based board. | 08:13 |
| _florent__ | futarisIRCcloud: i think this Avalanche link use the new VexRiscv: https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-avalanche.html# | 08:13 |
| tpb | Title: Running 32-bit Linux on Litex/VexRiscv on Avalanche board with Microsemi PolarFire FPGA RISC-V - Getting Started Guide (at risc-v-getting-started-guide.readthedocs.io) | 08:13 |
| futarisIRCcloud | Oh, didn't see they rebuilt it. | 08:15 |
| keesj | for adding a clock definition.... somewhere the magic happens to add add_clock in the top.xdc (I think depending on the existance of the default_clk_period but there are also cases where the clock is added using platform commands | 08:19 |
| keesj | (in my case the magic does not happen) | 08:20 |
| daveshah | Wonder if the boot time on the Avalanche is partly related the the AXI bridge between the SoC and the Microsemi DDR IP | 08:20 |
| _florent__ | daveshah: yes that's possible, it would need to be investigated. It seems even the targets with 16-bits SDRAM and slow clock freq are booting faster... | 08:45 |
| Dolu | Just one thing to keep in mind about the CPU, is that it is actualy a write-through data cache. So, each software store will end up with one memory request on the wishbone dBus | 08:57 |
| futarisIRCcloud | The GOWIN / Anlogic FPGAs seem to be cheap too. Sipeed Tang should be able to run vexriscv and linux. 8MB SDRAM on the same IC. | 09:32 |
| _florent__ | futarisIRCcloud: thanks, that's indeed cheap | 09:50 |
| _florent__ | keesj: you need to use add_period_constraint to add a clock constraint | 09:53 |
| keesj | cool thanks! | 11:08 |
| keesj | how long is the sim.py test expected to take? (it has been running for a few hours now) | 12:10 |
| Dolu | keesj, which sim exactly ? the linux one ? | 12:43 |
| keesj | well sim in litedram (examples/sim) that one (running under linux) used the vivado xsim. I think it might be running 4 ever. I interrupted and it shutdow mostly gracefully | 13:54 |
| keesj | hmm it is gone in the main repository https://github.com/enjoy-digital/litedram/commit/b93412bbdc116e4b59023e129103c5ed29bf5844 | 13:55 |
| tpb | Title: examples: remove verilog simulation · enjoy-digital/litedram@b93412b · GitHub (at github.com) | 13:55 |
| keesj | 5 days ago | 13:56 |
| keesj | _florent__: I fixed the clock warning and can trace some signals (ODT and BA2 for example) but still not the RAS,CAS,WE signal I am starting to suspect signal integrity problems | 14:59 |
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| _florent__ | keesj: i indeed removed the sim, it was not working as commited and was just here to provide an example of how to generate the core and run it with xsim | 21:56 |
| _florent__ | keesj: but some modules were missing | 21:56 |
| _florent__ | the best is to generate the full core and just simulate it, but i can be a bit slow | 21:56 |
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