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| somlo | _florent__: trying to generate a dram controller with exposed CSR bus, and I'm wondering what I screwed up (https://github.com/gsomlo/litedram/tree/gls-expose-csr) | 11:21 |
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| tpb | Title: GitHub - gsomlo/litedram at gls-expose-csr (at github.com) | 11:21 |
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| somlo | oh, when cpu_type="None" there are no wishbone masters, so the entire block where CSR regions are generated and connected to the bus is skipped in SoCCore's do_finalize :) | 13:04 |
| somlo | _florent__: I'll try to cook up a patch that executes some part of this block (https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L483) if self.csr_expose is true, regardles of whether there are any self._wb_masters :) | 13:15 |
| tpb | Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com) | 13:15 |
| _florent__ | somlo: i was just looking at it | 13:16 |
| _florent__ | somlo: i'm doing the changes | 13:17 |
| somlo | ok, cool, thanks! | 13:17 |
| somlo | like, self.csr will be the only master on the csr_bus.Interconnect, or something | 13:18 |
| _florent__ | somlo: https://github.com/enjoy-digital/litex/commit/526ba1b165a09f6c0b51646a4b3124b345428d28 | 13:27 |
| tpb | Title: soc_core: remove csr_expose and add add_csr_master method · enjoy-digital/litex@526ba1b · GitHub (at github.com) | 13:27 |
| _florent__ | and | 13:27 |
| _florent__ | https://hastebin.com/huyeqacame.pl | 13:27 |
| somlo | nice, thanks! (you also caught my csr_port.dat_r typo :) ) | 13:35 |
| somlo | I guess for a complete "motherboard-on-a-chip" we'd also need to expose the interrupt pins... | 13:45 |
| somlo | _florent__: something like this, maybe: https://pastebin.com/22PDGAH9 | 15:27 |
| tpb | Title: [Diff] diff --git a/examples/litedram_gen.py b/examples/litedram_gen.py index 9450d39. - Pastebin.com (at pastebin.com) | 15:27 |
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| _florent__ | somlo: that could be useful for another generator, but here for LiteDRAM the peripherals/registers involved in the DRAM initialization don't have interrupts | 16:32 |
| somlo | I'm trying to generate a sort-of "motherboard-on-chip", i.e. all of LiteX minus the CPU :) | 17:17 |
| somlo | starting with the LiteDRAM generator, which generously throws in the uart "for free" | 17:17 |
| somlo | figured I'd expose the CSRs and interrupts, then I have all I need (working on adding ethernet in there as well) | 17:17 |
| somlo | so maybe it won't end up as a patch against the liteDRAM example generator, but I definitely think that's a very useful place to start :) | 17:19 |
| _florent__ | :) | 17:36 |
| somlo | that said, since you went through all that trouble to help me out with csr_expose, and since "None" is an option for the litedram example generator, let's at least consider this: https://github.com/enjoy-digital/litedram/pull/82 | 17:46 |
| tpb | Title: examples/litedram_gen: allow direct access to CSR (I/O) registers by gsomlo · Pull Request #82 · enjoy-digital/litedram · GitHub (at github.com) | 17:46 |
| somlo | the exposed IRQs (and ethernet, when I get done with it) can go somewhere else more appropriate, if and when :) | 17:47 |
| _florent__ | somlo: yes sure, we can merge this one | 17:48 |
| keesj | won't the core_config["expose_csr_port"] == "yes" check fail if the property is not defined? | 18:44 |
| somlo | keesj: you're right, let me go google the canonical Python way to handle this (it's not my "native tongue" :) ) | 19:06 |
| somlo | keesj: I think I figured it out, thanks for catching it! | 19:14 |
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| keesj | nice | 19:38 |
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| femto | Howdy! Anyone else experience gateware-flash size issues on the TinyFPGA BX? (GitHub Issue: https://github.com/timvideos/litex-buildenv/issues/137 ) | 22:15 |
| tpb | Title: make gateware-flash "FAILED!" on TinyFPGA BX · Issue #137 · timvideos/litex-buildenv · GitHub (at github.com) | 22:15 |
| mithro | femto: Hi! | 22:18 |
| mithro | femto: I have seen this before | 22:18 |
| femto | mithro Where is a good place to start checking? Should I examine tinyprog? Or perhaps litex-buildenv? | 22:25 |
| mithro | femto: I think the issue has something to do with the byte pattern and tinyusb's usb stack | 22:25 |
| mithro | femto: It seems to go away if you just change the firmware slightly... | 22:26 |
| femto | mithro: modify the firmware? as in litex-buildenv/firmware? | 22:27 |
| mithro | femto: Yeah.... | 22:27 |
| femto | mithro: Ok, I'll attempt to edit a C header or something, and reattempt "make gateware-flash" | 22:28 |
| mithro | femto: Maybe... | 22:28 |
| femto | mithro: what type of edits got it working for you? (I'm assuming unused code and comments are parsed out by the compiler, and don't affect the binary) | 22:42 |
| mithro | femto: Unclear at the moment -- cr1901_modern and ewenz in #timvideos are the people who have played with it the latest | 22:44 |
| femto | mithro: ah ok, I'll go ask | 22:44 |
| femto | mithro: thank you! | 22:44 |
| mithro | femto: ewen is in the New Zealand timezone | 22:45 |
| mithro | femto: This person -> https://github.com/ewenmcneill | 22:45 |
| tpb | Title: ewenmcneill (Ewen McNeill) · GitHub (at github.com) | 22:45 |
| mithro | femo: Can you try with just the bios rather than micropython? | 22:46 |
| femto | mithro: I'm not familiar enough with litex-buildenv... is there a make command for just the bios or something? | 22:47 |
| mithro | femto: "unset FIRMWARE" and then "make gateware-flash" is probably the right move | 22:48 |
| femto | mithro: I thought "FIRMWARE" needed to be set to "tinyfpga_bx"... so it shouldn't be set? | 23:08 |
| mithro | femto: Can you type "make info" | 23:08 |
| femto | mithro: whoops.. I misspoke, FIRMARE=micropython, PLATFORM=tinyfpga_bx | 23:11 |
| femto | mithro: | 23:11 |
| femto | make info | 23:11 |
| femto | Platform: tinyfpga_bx | 23:11 |
| femto | Target: base (default: base) | 23:11 |
| femto | CPU: lm32.minimal (default: lm32) | 23:11 |
| femto | Firmare: micropython (default: firmware) | 23:11 |
| mithro | Yeah, try unsetting the firmware value | 23:32 |
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