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futarisIRCcloud | https://mindchasers.com/dev/darsena-shield | 01:32 |
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tpb | Title: The Darsena Shield for Arduino (at mindchasers.com) | 01:32 |
futarisIRCcloud | http://ipusltd.com/Products_en.html | 03:19 |
tpb | Title: IPUS Limited : Products (at ipusltd.com) | 03:19 |
futarisIRCcloud | IPS6404L-SQ-SPN is aroiund $1 | 03:19 |
futarisIRCcloud | https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html | 06:28 |
tpb | Title: FreeRTOS for RISC-V RV32 and RV64 (at www.freertos.org) | 06:28 |
keesj | how is idelayctrl "combined" with idelay in litedram? | 09:11 |
keesj | the CRG create an idelayctrl (and but where is it used?) | 09:11 |
keesj | the warning I have when building arty (but also my target is ) WARNING: [Synth 8-350] instance 'IDELAYCTRL' of module 'IDELAYCTRL' requires 3 connections, but only 2 given [/home/why/projects/ddr3/litex/soc_basesoc_arty/gateware/top.v:9950] | 09:16 |
keesj | looking at the code indeed only the input clocks are used (no output signal) | 09:17 |
keesj | does that mean that the idelaycontrol is perhaps not working(would ddr work without it?) | 09:18 |
keesj | btw yesterday I reworked a 400+ BGA and the thing worked! | 09:18 |
keesj | hmm the third pin is just the ready pin... | 09:20 |
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_florent__ | keesj: the idelayctrl connections are not exposed to the fabric, so you just have to instanciate it and provide a 200MHz reference clock | 15:43 |
keesj | I scanned the other warnings but did not find real bad stuff | 16:11 |
keesj | a lot of warning about not all ports being used | 16:11 |
_florent__ | yes, you can safely ignore these warnings | 16:26 |
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Dolu | <3 https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-avalanche.html# <3 | 23:18 |
tpb | Title: Running 32-bit Linux on Litex/VexRiscv on Avalanche board with Microsemi PolarFire FPGA RISC-V - Getting Started Guide (at risc-v-getting-started-guide.readthedocs.io) | 23:18 |
Dolu | I'm just not sure why on some board it take so much time to boot. It probably need some investigation. | 23:23 |
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