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| keesj | Hi | 07:14 |
|---|---|---|
| Dolu | Hi | 08:17 |
| _florent__ | Hi | 09:25 |
| _florent__ | keesj: how is going your ISERDESE2 / DDR project? | 09:25 |
| keesj | I was a hack in the box last week hence not much progress. I was able to capture the ODT signal but was so far not able to capture the cas/ras/we signals.. I do not know why | 09:27 |
| _florent__ | ah ok thanks, i was just curious | 09:28 |
| keesj | I will first try understanding/fixing some warning I still have in the code (one about my clocks not well defined and and other about ... on of the d0 d6 needs to be connected | 09:31 |
| keesj | WARNING: [Power 33-232] No user defined clocks were found in the design! | 09:33 |
| _florent__ | for testing your code, maybe you should generate pre-defined patterns with the FPGA or an external equipment and verify that you see this with your analysis gateware/software | 09:33 |
| _florent__ | this means that you probably forgot to apply a clock constraint to the input clock pin | 09:34 |
| keesj | I first did that with the tinyfpga (until 48Mhz) but not my whole design is synced with the DDR clock | 09:34 |
| keesj | and I for example need to generate a 200Mhz clock for the idelday. | 09:35 |
| _florent__ | in your case, you need to apply timing constraint to the system clock and to the DDR clock (if you are using it to sample your data) | 09:37 |
| keesj | I have two boards so I indeed might be able to connect them togethers. but I also have other things I need to figure out .. like the SSTL135 IOStandard, just grounding or doing a pull up did not produce the expected result either | 09:37 |
| keesj | but I am quite happy to see that the wishbone serial is working and stuff so .. pretty cool so far | 09:38 |
| keesj | it is kinda crazy how much it working with some basic cut & paste | 09:43 |
| keesj | (and reading) | 09:46 |
| keesj | and .. I gave up (for now) on the 4:1 logic analyzer part. I think it would be a great demo/example code so have a fast logic analyzer | 09:51 |
| *** felix___ is now known as felix_ | 12:24 | |
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