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| keesj | pretty cool (mmu + linux) | 05:36 |
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| futarisIRCcloud | _florent__: Good job. I'll try and test on my Arty 35T sometime soon. | 07:00 |
| keesj | yea it is pretty cool. but in the end I am here to not do linux stuff and least not on the software side. looking at how the mmu is implemneted .. really cool | 07:12 |
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| _florent__ | keesj: you'll still be able to to do what you want with the hardware but will also the flexibility of Linux/Software for things that are tedious to do in hardware :) | 07:37 |
| keesj | yea.. it is more ... I started as Java programmer back in the 90's and been doing down the software supply chain ever since. Still remember how exited I was to create my first kernel driver | 07:41 |
| keesj | good old times | 07:41 |
| keesj | also good old times fighting the MMU when porting Minix3 to ARM | 07:43 |
| keesj | horray \o/ running running in sycn with ddr! | 09:44 |
| keesj | Still is it kinda strage my clock is fed through a DifferentialInput DIFF_SSTL135 but it looks like when no signal is present still somehow somewhere a clock is generated | 09:46 |
| Dolu | _florent__ I submited a fix to force the block ram inferation via attributes | 09:53 |
| Dolu | (in Vexriscv-Verilog) | 09:53 |
| _florent__ | Dolu: thanks, i'll test this afternoon | 09:54 |
| acathla | Heureusement qu'on sait tous quand à lieu ton afternoon ;) | 10:01 |
| _florent__ | :) | 10:06 |
| Dolu | _florent__ For the LUT usage, the bad VexRiscv area usages are only due to Vivado moving logic through hierarchy. I force him to not use cross hierarchy optimisations, and with the linux-minimal setting and you SoC, VexRiscv is 2451 LUT :) | 10:10 |
| Dolu | The non-minimal linux config (the one you have actualy) would probably use about 200 luts more. | 10:10 |
| keesj | m'enfin | 10:11 |
| Dolu | instruction cache is reported as 31 LUT, data cache as 253 LUT XD (with atomic) | 10:11 |
| _florent__ | Dolu: ok, regarding performance, is the linux-minimal equivalent to the linux one? | 10:12 |
| Dolu | Yes | 10:12 |
| Dolu | It avoid all the unused CSR features, especialy in the machine mode. | 10:13 |
| futarisIRCcloud | Which unused CSR? | 10:13 |
| _florent__ | ok, are we going to need these CSR in the future? | 10:13 |
| Dolu | For the supervisor, it only provide scycle and sinstret. | 10:17 |
| Dolu | I mean | 10:18 |
| Dolu | the linux-minimal remove the scycle and sinstret from supervisor capabilities, and delegate them to machine mode emulation. | 10:19 |
| Dolu | So, nothing which would sudently break compatibility with upstream linux, | 10:20 |
| _florent__ | ok, so you also adapted the emulator code? | 10:20 |
| Dolu | The emulator code is already ready to handle linux-minimal required emulations | 10:21 |
| Dolu | https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/c/emulator/src/main.c#L238 | 10:21 |
| tpb | Title: VexRiscv/main.c at master · SpinalHDL/VexRiscv · GitHub (at github.com) | 10:21 |
| _florent__ | ok | 10:21 |
| Dolu | That's not perfect as a RDINSTRET implementation, but for embedded FPGA stuff, i think that's good enough | 10:21 |
| futarisIRCcloud | Sounds fine for a single core on a FPGA. | 10:25 |
| _florent__ | Dolu: linux-minimal is working fine and resource usage is indeed reduced: https://hastebin.com/pefubupizo.rb | 10:39 |
| Dolu | Cool :) | 11:19 |
| keesj | _florent__ your help is very much appreciated! you turned my week from missery to happynes | 11:35 |
| keesj | is there a way I can request a subsignal without first getting the signal ? e.g. my clock is currently on a pmod so I o resource.request("pmodb") and then do pads.clp | 11:48 |
| keesj | but I need to use the same resource somewhere else | 11:49 |
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| _florent__ | keesj: no, you have to request the full ressource for now | 12:30 |
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| keesj | I will do some refactoring. it does not really matter but I think I migh also have already worked around it before by doing something like bla = Pins("E12") | 13:31 |
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