| *** tpb has joined #litex | 00:00 | |
| *** futarisIRCcloud has joined #litex | 00:38 | |
| keesj | \o/ I am at least getting something! | 06:52 |
|---|---|---|
| *** futarisIRCcloud has quit IRC | 09:17 | |
| *** futarisIRCcloud has joined #litex | 10:15 | |
| keesj | my plan now it to start the system from the ddr clock to be synchronized with it I hope I won't run into the same type of issues | 12:57 |
| keesj | can I create a crg | 13:16 |
| keesj | when I have no Soc? | 13:16 |
| keesj | I see GRC is "just" a submodule of a module or is it more complicated? | 13:16 |
| *** Dolu1990 has joined #litex | 13:56 | |
| keesj | so adding GRC as submodule is enough to change the sys_clk apparently :P.. cool | 14:08 |
| *** Dolu1990 has quit IRC | 16:29 | |
| *** miaou_ has joined #litex | 16:36 | |
| *** futarisIRCcloud has quit IRC | 16:47 | |
| somlo | \O/ http://www.contrib.andrew.cmu.edu/~somlo/BTCP/RocketLitexFirstTime_20190502.png | 17:00 |
| * somlo goes grepping for where he's supposed to provide a useful string to replace "Unknown" :) | 17:03 | |
| somlo | keyboard i/o doesn't work yet, but at this point I think it's a "Simple Matter of Programming" :) | 17:04 |
| somlo | _florent_: thanks again for the axi2wb fixes, it was the software trapping due to accessing the wrong Rocket risc-v CSR registers | 17:06 |
| _florent__ | somlo: great! | 17:07 |
| somlo | _florent_: I'm impressed at just how little hackery was actually needed to get it going -- LiteX Rocks!!! :) | 17:08 |
| * somlo found the #ifdef in main() where he should add printf "RocketRV64[imac]" | 17:10 | |
| somlo | next on the agenda is getting the simulation to accept keyboard input (most likely still just a software thing) | 17:11 |
| _florent__ | VexRiscv new MMU also rocks: https://asciinema.org/a/WfNA99RCdVi8kTPfzNTeoMTtY :) | 17:14 |
| tpb | Title: untitled - asciinema (at asciinema.org) | 17:14 |
| _florent__ | https://github.com/enjoy-digital/linux-on-litex-vexriscv | 17:14 |
| tpb | Title: GitHub - enjoy-digital/linux-on-litex-vexriscv: Experiments with Linux on LiteX-VexRiscv (at github.com) | 17:14 |
| _florent__ | ^ miaou_ | 17:15 |
| miaou_ | Hi, sorry for my name, i'm Dolu | 17:17 |
| miaou_ | Hoo nice :D | 17:18 |
| miaou_ | wtf XD | 17:19 |
| miaou_ | GG ! | 17:19 |
| *** Dolu has joined #litex | 17:19 | |
| Dolu | How the synthesis is running ? | 17:22 |
| Dolu | Hoo 100Mhz | 17:23 |
| *** miaou_ has quit IRC | 17:23 | |
| Dolu | Wasn't to much of a pain to get it working ? | 17:24 |
| _florent__ | no, i just adapted things progressively with the simulation (mostly reusing LiteX peripherals and adapting the emulator code) | 17:28 |
| _florent__ | then i tested on hardware and it just worked :) | 17:28 |
| Dolu | 5.0.9, Yeahhhhhh 4.20.17 is so borring ^.^ | 17:29 |
| Dolu | Nice :D | 17:30 |
| Dolu | it was probably pleasant :p | 17:31 |
| _florent__ | i just wanted to be sure it was working with upstream version of all the tools :) | 17:31 |
| Dolu | About synthesis, things were looking good ? | 17:32 |
| Dolu | frequancy, area usage and stuff like this ? | 17:32 |
| _florent__ | timing is fine yes on the XC7A35T of the Arty | 17:35 |
| _florent__ | here is the resource usage: https://hastebin.com/wuhikehego.rb | 17:36 |
| Dolu | Hmm there is synthesis issues | 17:37 |
| Dolu | the instruction cache and data cache are way too big | 17:37 |
| Dolu | It didn't all infered the caches ram as ram blocks | 17:38 |
| _florent__ | ok, i can look at the vivado report | 17:39 |
| _florent__ | btw, if you want to look, you can generate the bitstream by just executing: https://github.com/enjoy-digital/linux-on-litex-vexriscv/blob/master/arty.py | 17:39 |
| tpb | Title: linux-on-litex-vexriscv/arty.py at master · enjoy-digital/linux-on-litex-vexriscv · GitHub (at github.com) | 17:39 |
| Dolu | As a estimate, the instruction cache should be about 200 lut, and the data cache about 600 lut (with atomic) | 17:39 |
| Dolu | Sure, i will look at it | 17:40 |
| Dolu | I can reproduce the issue, thanks for flow ^^. When i have a fix i will tell you. | 18:12 |
| Dolu | ^ _florent__ The VexRiscv.v was generated with sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux" ? | 18:16 |
| Dolu | Also forcing using ram blocks for the caches reduced the LUT usage by 800 LUT, but there is still something wrong, still 1K lut getting somewhere it shouldn't, especialy the instruction cache. | 18:18 |
| Dolu | Ahhh, https://github.com/enjoy-digital/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenCoreDefault.scala#L167 could have been linuxMinimal, should save about 300 LUT, i will give a try | 18:23 |
| tpb | Title: VexRiscv-verilog/GenCoreDefault.scala at master · enjoy-digital/VexRiscv-verilog · GitHub (at github.com) | 18:23 |
| daveshah | Just tried building for Versa ECP5 and it still meets timing at 75MHz which is good (usage is horrible because of unsupported DSP inference, but we'll hopefully sort that soon). Will test on hardware tomorrow and submit a PR if it is working | 18:24 |
| daveshah | Boot time looks about 10-20x faster than with the previous MMU which is awesome | 18:25 |
| Dolu | Hoo good :) | 18:25 |
| Dolu | Great | 18:25 |
| Dolu | Let's me know how things goes ! | 18:25 |
| daveshah | Had to reduce emulator ram size from 0x10000 to 0x8000 because it ran out of BRAM | 18:25 |
| Dolu | Also, Multiplication can be changed to be iterative without DSP | 18:25 |
| Dolu | (rebooting my PC) | 18:26 |
| *** Dolu has quit IRC | 18:26 | |
| *** Dolu1990 has joined #litex | 18:28 | |
| xobs | daveshah: DSP inference? Do say more. Are those similar DSP blocks to the ICE40? | 18:38 |
| daveshah | No, they are quite different | 18:52 |
| daveshah | But there should be some more work on DSP stuff in general soon (in particular things like splitting larger multiplies) | 18:52 |
| daveshah | Once that's moved on a bit I'll look at adding ECP5 support | 18:53 |
| xobs | Well hooray! Looking forward to that. | 18:54 |
| *** Dolu1942 has joined #litex | 19:13 | |
| *** Dolu1990 has quit IRC | 19:16 | |
| Dolu1942 | ^ daveshah adding --singleCycleMulDiv false to the arguments of the VexRiscv generation would solve it. | 19:17 |
| _florent__ | Dolu1942: yes, i was using sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux" | 19:33 |
| Dolu1942 | Hoo about the emulator memory requirements, they are oversized | 21:02 |
| Dolu1942 | The stack do not need to be big at all | 21:02 |
| _florent__ | yes, i will reduce that | 21:06 |
| Dolu1942 | Also, one thing which isn't implemented in the machine mode emulator, is the unaligned access emulation | 21:43 |
| Dolu1942 | Currently if a unaligned access is done, where ever it is, it will come back t the machine mode and exit everything. | 21:44 |
| Dolu1942 | Should the emulator emulate the unaligned load/store ? or it should propagate the exception to the supervisor ? | 21:45 |
| *** Dolu1942 has quit IRC | 22:28 | |
| *** Dolu has joined #litex | 22:30 | |
| Dolu | _florient__ Going from CSR linuxFull to linuxMinimal reduced the LUT occupancy by 800 XD | 23:14 |
| Dolu | Combined with the ram block forcing, the total VexRiscv LUT usage is downto 2665 | 23:14 |
| Dolu | linuxMinimal https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L82 vs linuxFull https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L122 | 23:15 |
| tpb | Title: VexRiscv/CsrPlugin.scala at master · SpinalHDL/VexRiscv · GitHub (at github.com) | 23:15 |
| Dolu | Ahhh mybad not exactly | 23:26 |
| *** Dolu has quit IRC | 23:55 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!
