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| futarisIRCcloud | https://www.mail-archive.com/[email protected]/msg610224.html | 01:54 |
|---|---|---|
| tpb | Title: [Qemu-devel] [PATCH for 4.1 v3 0/6] RISC-V: Allow specifying CPU ISA via command line (at www.mail-archive.com) | 01:54 |
| futarisIRCcloud | https://www.mail-archive.com/[email protected]/msg611889.html | 01:55 |
| tpb | Title: [Qemu-devel] [PATCH v1 0/6] RISC-V: Add properties to the CPUs (at www.mail-archive.com) | 01:55 |
| futarisIRCcloud | https://www.youtube.com/watch?v=FyqOYnkXsj0 | 02:29 |
| futarisIRCcloud | Intel x86 on RISC-V - Qemu ception | 02:30 |
| keesj | Morning | 06:19 |
| futarisIRCcloud | Hi | 06:41 |
| keesj | I need to find a way to speedup my experiments. I am starting to get somewhere but it takes minutes to compile the bit file and I can not really do anything but wait else I get into a context switch | 06:44 |
| futarisIRCcloud | litex simulator (with the bridge) ??? | 07:29 |
| keesj | perhaps | 09:16 |
| keesj | I did a little testing using python when following the tutorial and tried to understand a few times how to test the serdes but I still don't quite get it | 09:26 |
| keesj | https://paste.ubuntu.com/p/FYyY8mDSWt/ I am trying to follow the xapp1017 notes http://paste.ubuntu.com/p/X83dWTtyrt/ (my current code) | 09:26 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 09:26 |
| _florent__ | keesj: yes, with vivado, even a very simple design takes a couple of minutes to compile... | 10:27 |
| _florent__ | keesj: this is one of the case where open-source toolchains are really interesting, a very simple design takes seconds and it ease doing multiple iterations... | 10:28 |
| _florent__ | i see that you also reduced your design to something small, so you will not gain a lot in compile time | 10:29 |
| _florent__ | keesj: you are using an IDELAYE2 before the ISERDESE2, so p_IOBDELAY="NONE" is wrong. XAPP1017 is using "IFD" | 10:37 |
| keesj | I was using ifd but ... then I get an other error about my O port (will compile and test again) | 10:45 |
| keesj | with ghdl (using vhdl and good test benches) I was also able to do quick tests (when doing my can bus stuff) but once I start using special blocks.... not great | 10:47 |
| keesj | with IFD I am getting ERROR: [DRC PDIL-1] Invalid Site Configuration: Invalid configuration for site ILOGIC_X0Y76. Reason: Site pin to site pin route-thru requires conflicting attribute enum values for user logic element 'ISERDESE2 in site 'ILOGIC_X0Y76'. Attribute 'IOBDELAY' is programmed to 'IFD' but needs a value of 'NONE' for the route-thru. | 10:47 |
| keesj | it has been almost a week now of reading . "a ha" moments" and trial and error. One thing that might be more usefull for the general public is if I first try to create a damm fast logic analyzer using internal clock and iserdes2 | 10:50 |
| keesj | and my understanding of the blocks is not good enough to write a stub | 10:56 |
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| keesj | https://hackaday.com/2018/03/22/a-diy-nine-channel-digital-scope/ | 13:35 |
| _florent__ | keesj: i just had another look at your code | 19:22 |
| _florent__ | your issue is probably due to the fact that you are connecting nwe to the ISERDESE2 and LiteScope | 19:23 |
| _florent__ | this signal can only go to the ISERDESE2, it's not possible to observe it with LiteScope | 19:24 |
| keesj | ahmmm | 19:44 |
| keesj | I will defenitely give it a try. I think I tried this already but I did not really inspect the generated to to know what is going on under the hood. in this case I would need to not define a self.nwe but only directly use pads.new or similar | 19:47 |
| keesj | I also was thinking perhaps I need to take little baby steps . first capture 8 lines at 100 Mhz (the curent setup) next try the same at 200Mhz ,then move to 400Mhz serdes 1:2 SDR mode (all as example of the logic analyzer) | 19:50 |
| keesj | It would be very helpfull for the sustainability of my project to have a litle more progress | 19:51 |
| keesj | the code does generate something like assign mux_endpoint1_payload_data = {nwe_buf, ddr_nwe} indeed | 19:56 |
| keesj | _florent__: the warning is now indeed gone... I can not test it right now crossing fingers! | 20:03 |
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