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| Adrien[m] | I'm not familiar with ecp5 DSPs, but this behaviour could be a different number of pipeline regs within the DSP for data inputs and for the SIGNED inputs | 11:25 |
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| gatecat | it's a shame the lattice sim models for the DSPs are such a mess | 12:15 |
| gatecat | maybe I should still try and see if I can figure out anything there | 12:16 |
| gatecat | can't reproduce this with a quick testbench using their sim model, so I guess it would be hardware testing time to investigate this further... | 12:27 |
| gatecat | https://usercontent.irccloud-cdn.com/file/NIBpPjZi/image.png | 12:27 |
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| juri_ | gatecat: do keep us posted, I'm just assembling a lattice test machine myself. | 22:44 |
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