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| Adrien[m] | Yes it does. when run without -wideluts. | 05:36 |
|---|---|---|
| Adrien[m] | This `mux8` error is weird, I will look at the netlist. | 05:36 |
| lofty | well, the error you posted was that it couldn't place a cell named "mux8" | 05:47 |
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| Adrien[m] | Debugging a bit, the cell type is `SELMUX2_1` | 08:41 |
| Adrien[m] | I'm not sure what behaviour to expect from nextpnr, is it supposed to decide to place this in a LUT or in a MUXF location ? | 08:41 |
| lofty | Adrien[m]: uuuh, I think this is where you have to show your source verilog, because that's not a valid cell | 08:42 |
| Adrien[m] | Yes. Need to reduce the design to something reproducer-friendly then. | 08:45 |
| Adrien[m] | Interestingly, nextpnr-xilinx does handle this design. | 08:45 |
| lofty | okay, it apparently *is* a valid bel type, but hmm | 08:49 |
| Adrien[m] | And I find no occurrence of selmux in input json ! | 08:50 |
| Adrien[m] | From the nextpnr-hibaechel log :... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/TPDvTLLAzyRNgUAKnfhsVShr>) | 08:52 |
| Adrien[m] | I'll reduce the design to something smaller | 08:55 |
| Adrien[m] | maybe just a mux 8->1 is enough | 08:55 |
| Adrien[m] | Had to do a mux 31->1 to ensure yosys generates a muxf7.... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/aoqVEbTJfBVlsQzvUZlynAxq>) | 09:47 |
| Adrien[m] | yosys -p "synth_xilinx -arch xc7 -top zedboard_top_mux; write_json zedboard_top_mux.json" zedboard_top_mux.v | 09:48 |
| Adrien[m] | nextpnr-himbaechel --device xc7z020clg484-1 -o xdc=zedboard.xdc --json zedboard_top_mux.json -o fasm=zedboard_top_mux.fasm --router router1 | 09:50 |
| Adrien[m] | The xdc file : https://gricad-gitlab.univ-grenoble-alpes.fr/prostboa/zynq-foss/-/raw/main/xdc/zedboard.xdc?ref_type=heads | 09:51 |
| Adrien[m] | If tracking of this is pertinent given development status, I can open an issue, please just say. | 09:55 |
| Adrien[m] | BTW I think this is also a Yosys sub-optimality | 09:57 |
| Adrien[m] | For a mux 8->1 it generates 3 LUTs, instead of 2 LUT6 + 1 muxf7 | 09:57 |
| Adrien[m] | Does this deserve to open an issue for yosys ? | 09:57 |
| lofty | Adrien[m]: what if you synth with -abc9 | 10:05 |
| lofty | actually | 10:06 |
| lofty | you want -widemux 8 to infer that | 10:07 |
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| Adrien[m] | lofty: most impactful option is indeed -widemux. not -abc9 for this topic. | 12:26 |
| lofty | Because -widemux does exactly what you ask for here, but it does come with headaches | 12:27 |
| Adrien[m] | ok good to know | 12:36 |
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| agg | bit of a long shot, but i'm using an ecp5 MULT18X18D with input and pipeline registers enabled and both SIGNEDIA/SIGNEDIB inputs hardwired to 1, and it seems to not sign-extend the first multiplication after a reset | 17:13 |
| agg | (with latest yosys/nextpnr-ecp5) | 17:13 |
| agg | anyone have... any ideas | 17:13 |
| agg | i haven't tried this on diamond so not entirely sure if it's specifically yosys/nextpnr or some cursed hardware thing though | 17:14 |
| whitequark[cis] | that's really cursed | 17:24 |
| agg | yea :( you can imagine it took a while it discover this was precisely what's going wrong too | 17:25 |
| agg | if i turn off the MULT18X18D's input registers and replace them with my own input registers instead, everything seems to work fine... | 17:34 |
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| whitequark[cis] | i wonder if there's a secret SIGNEDA reset register | 17:56 |
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