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| danderson | Hi! I need to write a sim model for ECP5's DP16KD. Beyond "look at what other FPGA memory sims do and be consistent with those", any docs/styles I should follow to make it a useful contrib to yosys? | 16:49 |
|---|---|---|
| danderson | I _think_ I understand the primitive's behavior enough to take a stab at the model, just wondering if there's any well known gotchas or style rules I should obey. | 16:50 |
| lofty | danderson: I think my advice would be to remember you're not writing a simulation model, as paradoxical as that is | 16:55 |
| lofty | Yosys will read and parse the sim model from a synthesis point of view, so if you throw in a bunch of simulation-specific things Yosys might just reject the model outright | 16:56 |
| danderson | lofty: hm, interesting. That complicates things a bit, because the model requires doing illegal things with clock domain crossing to detect misuses... | 17:44 |
| danderson | sounds like that might make yosys quite mad, or trigger incorrect optimizations? | 17:45 |
| danderson | I guess I'll start hacking and see how it does. I assume that means I should also not use '?' values to represent states where the hardware says the state is undefined? | 17:46 |
| danderson | Sounds like I should print a warning and pick a binary state instead | 17:46 |
| lofty | I assume that means I should also not use '?' values to represent states where the hardware says the state is undefined? <-- doing this is entirely okay | 18:43 |
| lofty | danderson: ^ | 18:44 |
| lofty | (although, I assume you mean 'x', and not '?' AKA 'z') | 18:44 |
| danderson | er yes sorry, I've been bouncing between languages too much. I mean the state to represent "you maybe just did a metastability, that's bad" :) | 18:46 |
| lofty | e.g. the Yosys memory inference code detects conditional x for at least one use case | 18:47 |
| danderson | right on. The other thing I'm not sure how to express is async reset and reset release, but my plan there was to look at other models and... generally go learn how to do it. | 18:51 |
| danderson | But I understand the internal memory layout and I think I know how to detect the read-write and write-write port conflicts, which I think are the main spicy parts of this primitive. | 18:52 |
| danderson | thanks for the wisdom! | 18:52 |
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