| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 00:21 | |
| *** Degi <[email protected]> has joined #litex | 00:22 | |
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 00:51 | |
| *** TMM_ <[email protected]> has joined #litex | 00:51 | |
| *** bl0x_ <[email protected]> has joined #litex | 01:22 | |
| *** bl0x <[email protected]> has quit IRC (Ping timeout: 252 seconds) | 01:23 | |
| *** toshywoshy <toshywoshy!~toshywosh@ptr-377wf33o3bnthuddmycb.18120a2.ip6.access.telenet.be> has quit IRC (Ping timeout: 264 seconds) | 01:41 | |
| *** toshywoshy <toshywoshy!~toshywosh@ptr-377wf33o3bnthuddmycb.18120a2.ip6.access.telenet.be> has joined #litex | 02:03 | |
| *** nickoe <[email protected]> has quit IRC (Quit: Client closed) | 02:21 | |
| *** nickoe <[email protected]> has joined #litex | 02:21 | |
| *** nickoe <[email protected]> has quit IRC (Quit: Client closed) | 06:00 | |
| *** nickoe <[email protected]> has joined #litex | 06:00 | |
| *** FabM <[email protected]> has joined #litex | 06:58 | |
| _florent_ | tpw_rules: With SDRAM, we indeed do not have automatic clock phase calibration, so this need to be adjusted from board to board (as you saw with your fix). | 07:11 |
|---|---|---|
| _florent_ | tpw_rules: regarding memory inference, I would like to have proper memory specialization/generator in the future to be able to specialize for the architecture we are building for. For now we are just relying on the synthesis tool: Here is a N-KB memory, with M ports, please do your best with it :) | 07:14 |
| _florent_ | somlo: strange for the failing variant. It however seems to be deterministic since you have 1/2 of data errors. This would be interesting to see if we also reproduce it in simulation with similar DRAM, if so, it will be easier to understand/fix | 07:16 |
| _florent_ | somlo: This could be a Down/Up-Converter corner-case triggered by this variant. | 07:17 |
| *** indy <[email protected]> has quit IRC (Ping timeout: 252 seconds) | 09:19 | |
| *** indy <[email protected]> has joined #litex | 10:07 | |
| *** nickoe <[email protected]> has quit IRC (Quit: Client closed) | 10:13 | |
| *** nickoe <[email protected]> has joined #litex | 10:13 | |
| somlo | _florent_: both nexys_video and ecpix5 end up with a 128-bit wide LiteDRAM native port (they both have 512MB RAM, and use MT41K256M16 modules -- with "1:4" and "1:2" rates, respectively) | 12:08 |
| somlo | so the `d` in `fulld`, `linuxd`, `full4d`, etc. stands for 128-bit axi mem bus, specifically used on those boards to avoid width conversion | 12:09 |
| RowanG[m] | Could someone enlighten me regarding ECLKs in the ECP5 the lattice sysClock doc leaves me with questions... | 12:29 |
| RowanG[m] | So when a clock comes out of the PLL it's a PCLK. Currently I just use this PCLK in my design to also clock input/output flip flops and there doesn't seem to be an issue. | 12:30 |
| RowanG[m] | Now according to the PDF OP and OS also generate an ECLK. | 12:30 |
| RowanG[m] | How can I access it? | 12:30 |
| RowanG[m] | Or is that done "automatically" as in if use the OP/OS Clk it will use the ECLK for the IO flip flops? | 12:31 |
| gatecat | it's automatic if you connect it to one of the ECLK-connected ports | 12:50 |
| gatecat | I can't remember if that includes the IO ffs or just the 1:4/4:1 serialisation primitives etc that have an ECLK port | 12:50 |
| RowanG[m] | Thanks @gatecate | 13:23 |
| RowanG[m] | gatecat: | 13:23 |
| *** nickoe83 <[email protected]> has joined #litex | 15:12 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Quit: Leaving) | 15:26 | |
| *** zjason` is now known as zjason | 15:26 | |
| *** nickoe <[email protected]> has quit IRC (Quit: Client closed) | 15:34 | |
| *** nickoe <[email protected]> has joined #litex | 15:35 | |
| *** Guest11 <[email protected]> has joined #litex | 16:09 | |
| *** mikek_VA3TEC <mikek_VA3TEC!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has joined #litex | 16:10 | |
| Guest11 | Hi, has anyone every got PCIe working with a Virtex 7 VC707 board? | 16:10 |
| mikek_VA3TEC | Hill all, I know this is embarrassing, I got Litex to compile with VexriscV for the Deca Board. But when I run lxterm I get this error... :( | 16:12 |
| mikek_VA3TEC | Traceback (most recent call last): | 16:12 |
| mikek_VA3TEC | File "/usr/local/bin/lxterm", line 11, in <module> | 16:12 |
| mikek_VA3TEC | load_entry_point('litex', 'console_scripts', 'lxterm')() | 16:12 |
| mikek_VA3TEC | File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 490, in load_entry_point | 16:12 |
| mikek_VA3TEC | return get_distribution(dist).load_entry_point(group, name) | 16:12 |
| mikek_VA3TEC | File "/usr/lib/python3/dist-packages/pkg_resources/__init__.py", line 2853, in load_entry_point | 16:12 |
| mikek_VA3TEC | raise ImportError("Entry point %r not found" % ((group, name),)) | 16:12 |
| mikek_VA3TEC | ImportError: Entry point ('console_scripts', 'lxterm') not found | 16:12 |
| mikek_VA3TEC | Do I need to recompile and reinstall the lxterm executable? | 16:13 |
| Guest11 | is lxterm the same as litex_term ? | 16:13 |
| mikek_VA3TEC | yes.. | 16:13 |
| mikek_VA3TEC | oh wait | 16:13 |
| mikek_VA3TEC | hold on... | 16:13 |
| mikek_VA3TEC | no, you are right | 16:14 |
| mikek_VA3TEC | it's litex_term!! | 16:14 |
| Guest11 | (y) | 16:14 |
| mikek_VA3TEC | ok, well it's still not working... but it might be the wrong baud rate.. | 16:15 |
| mikek_VA3TEC | I was following this... https://github.com/DECAfpga/DECA_board/tree/main/Litex | 16:16 |
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 16:18 | |
| *** TMM_ <[email protected]> has joined #litex | 16:18 | |
| Guest11 | then "litex_term --speed 115200 /dev/ttyUSB0" should work | 16:20 |
| Guest11 | but that board uses a JTAG-UART!? So you might need the "--jtag-name" parameter for litex_term, not sure though. According to the readme not. Correct USB port selected? | 16:22 |
| mikek_VA3TEC | So I am using the external serial... GPIO serial.. | 16:23 |
| mikek_VA3TEC | #GPIO Serial | 16:23 |
| mikek_VA3TEC | #Subsignal("tx", Pins("P8:3")),-> pin 03 (White C96 cable) GPIO0_D0 | 16:23 |
| mikek_VA3TEC | #Subsignal("rx", Pins("P8:4")),-> pin 04 (Green C96 cable) GPIO0_D1 | 16:23 |
| mikek_VA3TEC | but i could be wrong.. | 16:25 |
| mikek_VA3TEC | I run this.... ./terasic_deca_mike.py --uart-name=gpio_serial --build --load | 16:25 |
| mikek_VA3TEC | well this one instead ./terasic_deca.py --uart-name=gpio_serial --build --load | 16:26 |
| mikek_VA3TEC | recompiling.... | 16:26 |
| mikek_VA3TEC | I also could have my tx - rx reversed.. | 16:26 |
| mikek_VA3TEC | GOT IT!!!!! | 16:27 |
| mikek_VA3TEC | Guest!!! Your a genius!!! | 16:27 |
| Guest11 | nice | 16:28 |
| mikek_VA3TEC | now i need to get a boot medium... Any idea's?? | 16:28 |
| mikek_VA3TEC | How Do i Load DOOM? | 16:28 |
| mikek_VA3TEC | I think Bruno Levy has something.. | 16:29 |
| Guest11 | litex_term --doom ? | 16:29 |
| mikek_VA3TEC | i need the linux bin file... | 16:29 |
| mikek_VA3TEC | BRB lunch ready... Thanks again!!! :) smiles... | 16:30 |
| *** Guest11 is now known as VC707 | 16:37 | |
| VC707 | Has anybody every used me with Litex? | 17:07 |
| mikek_VA3TEC | ME? | 17:07 |
| VC707 | no anybody at all. The only thing that is working for me is the UART and DRAM | 17:08 |
| VC707 | no PCIe | 17:08 |
| mikek_VA3TEC | same here | 17:08 |
| mikek_VA3TEC | which board? | 17:08 |
| VC707 | VC707 | 17:08 |
| mikek_VA3TEC | woah... that a big board | 17:09 |
| mikek_VA3TEC | 5.2K? | 17:09 |
| mikek_VA3TEC | do you compile anything with it? did you look at the verilog code? | 17:10 |
| VC707 | 5.2€ ? Sounds about right but bought by the University | 17:10 |
| VC707 | Yes I did, I also applied constraints from a Xillybus design that is known to work with exactly that board. I guess that made it worse, now it crashes the PC :D but before that, I only got 0xFF from the board | 17:11 |
| mikek_VA3TEC | what your Litex command line that you are using? you have the enable a lot of stuff I think.. | 17:11 |
| VC707 | I just need a fast way to transfer data from a host to the DRAM of the board | 17:11 |
| VC707 | and back | 17:11 |
| mikek_VA3TEC | any jtag ports? | 17:12 |
| mikek_VA3TEC | you can run a GPIO at like 1Megabuad.. you just have to specify it in litex target file.. | 17:13 |
| VC707 | the xilinx_vc707.py has a "--with-pci" toggle but that is broken, after fixing it and other constraints, its generating the bit file | 17:13 |
| mikek_VA3TEC | cool... Did you do a pull request to Florent? | 17:13 |
| VC707 | With the jtagbone it appears to be writing fast (about 10MB/s), but reading is super slow. | 17:14 |
| VC707 | not yet | 17:14 |
| VC707 | and sometimes it has timeout errors | 17:14 |
| mikek_VA3TEC | Ah cool Good, Did you calibrate the Ram?? mmight be something with that... | 17:14 |
| mikek_VA3TEC | again I am still learning... | 17:14 |
| VC707 | that is done automatically, the DRAM works fine | 17:15 |
| mikek_VA3TEC | what do you get for a data rate? Around 10MB/s? just curious.. | 17:15 |
| VC707 | 80MB/s read and write from the C app running on the default Virtex CPU | 17:16 |
| mikek_VA3TEC | oh yeah, I meant with Litex... are you able to do a calibration of the ram that way? or it's automatic... | 17:17 |
| VC707 | the RAM calibration is done with a snippet of C-code that is provided by litex. | 17:19 |
| mikek_VA3TEC | and your Ram reads were good.... I am assuming... yup beyond me... Sorry wich i can help.. | 17:20 |
| VC707 | yes they work well, transfer with UART is also fine but slow (80KB/s) | 17:21 |
| mikek_VA3TEC | I am still struggling with getting a demo bin file to run... :( | 17:21 |
| mikek_VA3TEC | what speed did you connect with? | 17:21 |
| mikek_VA3TEC | 115200? | 17:22 |
| VC707 | 950xxx | 17:22 |
| VC707 | 2M worked at some point but then stoppen working | 17:22 |
| VC707 | I have a shorter cable now, maybe I try again | 17:23 |
| mikek_VA3TEC | yes.. ok good.. But with the higher bit rates i find the grounding and shielding is very important... | 17:23 |
| mikek_VA3TEC | yes... | 17:23 |
| mikek_VA3TEC | shorter cable and really good shielding and grounding.. | 17:23 |
| mikek_VA3TEC | any EMI in the area will kill your data rate... | 17:23 |
| VC707 | okay not the front USB ports, got it | 17:24 |
| mikek_VA3TEC | Also, if you can change your data rate but a few kilohertz you might be at a harmonic of power line... etc.. | 17:24 |
| mikek_VA3TEC | or any inverters or switching power supplies... | 17:25 |
| mikek_VA3TEC | if you have a Spectrum analyzer around... see what's going in the lab.. but that''s a bit of overkill... | 17:26 |
| mikek_VA3TEC | for me I twist the TX amd RX together... but you may not be able to do that. depending on the cables.. | 17:27 |
| VC707 | I have just a regular USB cable | 17:28 |
| mikek_VA3TEC | hummm.... how are you changing the speed? | 17:30 |
| mikek_VA3TEC | what target file do you have? | 17:30 |
| mikek_VA3TEC | oh wait got it | 17:30 |
| VC707 | --uart-baudrate 2764800 :D | 17:32 |
| mikek_VA3TEC | yup.. good try a little lower... 2764400 or 2764000... but at this point shot's in the dark.. | 17:33 |
| VC707 | I'll try, thanks | 17:34 |
| mikek_VA3TEC | where do you change the actual bitrate... I am trying to remember? | 17:36 |
| mikek_VA3TEC | i know that i chaned it in the target file... | 17:36 |
| mikek_VA3TEC | Oh I remember now... it's in :q! | 17:38 |
| mikek_VA3TEC | oops | 17:38 |
| mikek_VA3TEC | linux-on-litex-vexriscV/soc_linux.py | 17:39 |
| mikek_VA3TEC | Any Luck?? | 18:07 |
| mikek_VA3TEC | @VC707 | 18:07 |
| VC707 | 2764000 and 2764800 are misses, I'll try 2764400 now | 18:16 |
| mikek_VA3TEC | These are just shot int he dark guesses... | 18:22 |
| mikek_VA3TEC | you can go a lot lower... 2Mb/s | 18:23 |
| somlo | _florent_: on second thought, it *might* have something to do with width conversion. I built a `linux` (64-bit memory axi port, which would have to be up-converted to the 128-bit liteDRAM port) -- memtest passed, kernel booted, but I started getting weird errors communicating with the sdcard | 18:34 |
| somlo | then I built a `linuxq` (256-bit memory axi port, which needs to be down-converted to the 128-bit liteDRAM port -- this is on a nexys_video) | 18:35 |
| somlo | here I got a failing memtest, never made it to booting linux | 18:35 |
| somlo | anyhow, I'll update issue #1432 so there's a record of all this experimentation :) | 18:36 |
| somlo | I wonder if I can find an older (pre-AXI-overhaul) commit in LiteX that still builds (might run into trouble failing to find a matching point-in-time commit for all the other bits and pieces, like litedram, litesata, litesdcard, etc.) | 18:44 |
| somlo | ... and bisect from there | 18:44 |
| somlo | the advantage of having a single repo with lite[sata|dram|sdcard|etc.] in subdirectories might be that one can have a much easier time bisecting for regressions | 18:44 |
| somlo | since those bits are in separate repositories, it's hard "synchronizing" while jumping around in the main litex repo during a bisect | 18:45 |
| *** nickoe83 <[email protected]> has quit IRC (Quit: Client closed) | 19:04 | |
| *** nickoe83 <[email protected]> has joined #litex | 19:04 | |
| *** VC707 <[email protected]> has quit IRC (Quit: Client closed) | 19:05 | |
| nickoe83 | I just build a pmod for usb to work with the kwargs["uart_name"] = "usb_acm" i.e. the valentyusb.usbcore. It appears to work great, but when I do reboot in the serial console it will not reconnect? Why could this be? | 19:20 |
| *** nickoe83 <[email protected]> has quit IRC (Quit: Client closed) | 19:22 | |
| *** nickoe36 <[email protected]> has joined #litex | 19:23 | |
| *** nickoe36 <[email protected]> has quit IRC (Client Quit) | 19:23 | |
| nickoe | Ok, on better nick now.. | 19:23 |
| mikek_VA3TEC | How many nick are there? :) | 19:24 |
| nickoe | one true only me :) | 19:25 |
| mikek_VA3TEC | 36 or 83 of you! :) | 19:27 |
| mikek_VA3TEC | I am trying to upload a kernel.bin file but it keeps failing... | 19:27 |
| mikek_VA3TEC | do I have specify the speed every time?? | 19:27 |
| mikek_VA3TEC | well demo.bin | 19:28 |
| mikek_VA3TEC | I am using litex_term.. | 19:28 |
| mikek_VA3TEC | CRC error | 19:28 |
| nickoe | Hmm, on my other computer it does appear to work ok. I use tio for the terminal. | 19:28 |
| nickoe | mikek_VA3TEC Is it over uart? | 19:29 |
| nickoe | The default should be 115200 IIRC | 19:29 |
| mikek_VA3TEC | well GPIO uart | 19:29 |
| mikek_VA3TEC | I get the Litex> prompt. | 19:29 |
| nickoe | If using something other than 115200 you may need to specify it | 19:29 |
| nickoe | hmm, ok | 19:29 |
| nickoe | What board are you using? | 19:29 |
| mikek_VA3TEC | Deca | 19:30 |
| nickoe | What does your commandline look like? | 19:30 |
| mikek_VA3TEC | litex_term /dev/ttyUSB0 --kernel=demo.bin | 19:30 |
| mikek_VA3TEC | do I need the external Ram for the VexriscV? | 19:31 |
| mikek_VA3TEC | I don;t think so?? | 19:31 |
| nickoe | I am not sure, but maybe you can build with something like --integrated-main-ram-size=0x8000 ? | 19:32 |
| mikek_VA3TEC | oh... right.... | 19:32 |
| mikek_VA3TEC | ok let me try that.. | 19:32 |
| nickoe | It is some time ago that I did this, I only just came back to play with this recently, so now I am just on a basys3 | 19:32 |
| nickoe | I have not tried to load non bootloader fw on it, but I saw that mentioned in the demo readme. | 19:33 |
| nickoe | But I am not able to build the demo because I get: | 19:33 |
| mikek_VA3TEC | no no, very good, That was a great suggestion!! | 19:33 |
| nickoe | https://dpaste.com/C7YLPQ428.txt which I don't quite understand | 19:34 |
| mikek_VA3TEC | Looks like your cross compiler is messed up | 19:34 |
| mikek_VA3TEC | can you just point to the RiscV one? | 19:35 |
| nickoe | Ahh, ok, I was using an older toolchain path for the commandline | 19:36 |
| mikek_VA3TEC | I use this for my RiscV | 19:36 |
| mikek_VA3TEC | export PATH=$PATH:/home/mikek/Documents/Cyclone5_SOC/Litex_directory/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin | 19:36 |
| *** Guest11 <[email protected]> has joined #litex | 19:38 | |
| mikek_VA3TEC | NICK!!! I get LiftOff now! | 19:38 |
| mikek_VA3TEC | but that it... | 19:38 |
| nickoe | I did this: | 19:38 |
| nickoe | #export PATH=~/litex/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin:$PATH | 19:38 |
| nickoe | export PATH=~/litex/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin:$PATH | 19:38 |
| nickoe | you may need a clean build when you add that arg | 19:38 |
| nickoe | and maybe you need to rebuild the demo.bin after it as well | 19:38 |
| mikek_VA3TEC | yes | 19:39 |
| nickoe | I had similar issues once, but I think the alignment is different. | 19:39 |
| mikek_VA3TEC | yup! | 19:39 |
| *** Guest11 is now known as VC707 | 19:39 | |
| nickoe | weeee donut via usb_acm | 19:40 |
| mikek_VA3TEC | SWEET!!! | 19:41 |
| mikek_VA3TEC | YES SIR!!! WORKING !!!! | 19:41 |
| mikek_VA3TEC | OWE you a beer my friend! | 19:42 |
| *** nickoe <[email protected]> has quit IRC (Quit: Client closed) | 19:49 | |
| *** nickoe <[email protected]> has joined #litex | 19:49 | |
| *** zjason` <zjason`[email protected]> has joined #litex | 19:53 | |
| *** zjason <[email protected]> has quit IRC (Ping timeout: 265 seconds) | 19:55 | |
| nickoe | mikek_VA3TEC great ! looking forward to it :D | 19:59 |
| nickoe | happy that I could help | 19:59 |
| mikek_VA3TEC | :D | 19:59 |
| *** VC707 <[email protected]> has quit IRC (Quit: Client closed) | 20:00 | |
| *** Guest11 <[email protected]> has joined #litex | 20:01 | |
| mikek_VA3TEC | I have always said! Everyone from this channel is invited to my Cottage!!! | 20:04 |
| mikek_VA3TEC | :) | 20:04 |
| mikek_VA3TEC | Have a beer on my at my QTH. Seadoo and Solar powered electric Floating Dock!!! | 20:04 |
| *** Guest11 is now known as VC707 | 20:07 | |
| *** nickoe <[email protected]> has quit IRC (Quit: Client closed) | 20:12 | |
| *** nickoe <[email protected]> has joined #litex | 20:13 | |
| nickoe | mikek_VA3TEC that sounds like a floating toilet, but google has other suggestions | 20:13 |
| nickoe | that being "seadoo" | 20:13 |
| mikek_VA3TEC | it's a 12 foot x 12 foot dock that floast and you can take it into the middleof the lake! | 20:14 |
| nickoe | I assume you are in Ottawa... I am in Denmark, so quite a distance. | 20:19 |
| mikek_VA3TEC | your invited to Ottawa, and Quebec where the Cottage is! :) Next time you come to Canada. | 20:21 |
| mikek_VA3TEC | :) | 20:21 |
| nickoe | thank you :) | 20:22 |
| *** mikek_ <mikek_!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has joined #litex | 20:53 | |
| *** mikek_ <mikek_!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has quit IRC (Client Quit) | 20:55 | |
| *** mikek_VA3TEC <mikek_VA3TEC!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has quit IRC (Ping timeout: 244 seconds) | 20:55 | |
| *** nickoe <[email protected]> has quit IRC (Quit: Client closed) | 23:13 | |
| *** nickoe <[email protected]> has joined #litex | 23:14 | |
| *** mikek_VA3TEC <mikek_VA3TEC!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has joined #litex | 23:17 | |
| mikek_VA3TEC | I Got my DECA Board to work with External SDRAM!! | 23:17 |
| mikek_VA3TEC | So proud! | 23:17 |
| mikek_VA3TEC | litex> mem_test 0x40000000 0x2000000 | 23:17 |
| mikek_VA3TEC | Memtest at 0x40000000 (32.0MiB)... | 23:17 |
| mikek_VA3TEC | Write: 0x40000000-0x42000000 32.0MiB | 23:17 |
| mikek_VA3TEC | Read: 0x40000000-0x42000000 32.0MiB | 23:17 |
| mikek_VA3TEC | Memtest OK | 23:17 |
| mikek_VA3TEC | litex> | 23:17 |
| mikek_VA3TEC | litex> mem_speed 0x40000000 0x2000000 | 23:17 |
| mikek_VA3TEC | Memspeed at 0x40000000 (Sequential, 32.0MiB)... | 23:17 |
| mikek_VA3TEC | Write speed: 15.6MiB/s | 23:17 |
| mikek_VA3TEC | Read speed: 22.1MiB/s | 23:18 |
| mikek_VA3TEC | litex> | 23:18 |
| tpw_rules | the litex memory access speed always seems kind of bad. is that just limited by the cpu then? i hope the caches would enable better bandwidth | 23:19 |
| mikek_VA3TEC | Well it's the MISTER External ram. I had to lower the clock rate to times 1... instead of X2. I was getting errors. | 23:21 |
| mikek_VA3TEC | not many but some... | 23:21 |
| mikek_VA3TEC | litex> | 23:21 |
| mikek_VA3TEC | litex> mem_test 0x40000000 0x2000000 | 23:21 |
| mikek_VA3TEC | Memtest at 0x40000000 (32.0MiB)... | 23:21 |
| mikek_VA3TEC | Write: 0x40000000-0x42000000 32.0MiB | 23:21 |
| mikek_VA3TEC | Read: 0x40000000-0x42000000 32.0MiB | 23:21 |
| mikek_VA3TEC | bus errors: 0/256 | 23:21 |
| mikek_VA3TEC | addr errors: 0/8192 | 23:21 |
| mikek_VA3TEC | data errors: 4/8388608 | 23:21 |
| mikek_VA3TEC | Memtest KO | 23:21 |
| mikek_VA3TEC | litex> | 23:21 |
| mikek_VA3TEC | litex> mem_test 0x40000000 0x2000000 | 23:21 |
| mikek_VA3TEC | Memtest at 0x40000000 (32.0MiB)... | 23:21 |
| mikek_VA3TEC | Write: 0x40000000-0x42000000 32.0MiB | 23:21 |
| mikek_VA3TEC | Read: 0x40000000-0x42000000 32.0MiB | 23:22 |
| mikek_VA3TEC | bus errors: 0/256 | 23:22 |
| tpw_rules | but still, that's 50MT/s i assume | 23:22 |
| mikek_VA3TEC | addr errors: 0/8192 | 23:22 |
| mikek_VA3TEC | data errors: 1/8388608 | 23:22 |
| mikek_VA3TEC | Memtest KO | 23:22 |
| mikek_VA3TEC | litex> | 23:22 |
| tpw_rules | btw please do not paste large blocks into IRC. it's annoying and can get you kicked | 23:22 |
| mikek_VA3TEC | litex> | 23:22 |
| mikek_VA3TEC | litex> mem_test 0x40000000 0x2000000 | 23:22 |
| mikek_VA3TEC | Memtest at 0x40000000 (32.0MiB)... | 23:22 |
| mikek_VA3TEC | Write: 0x40000000-0x42000000 32.0MiB | 23:22 |
| mikek_VA3TEC | Read: 0x40000000-0x42000000 32.0MiB | 23:22 |
| mikek_VA3TEC | bus errors: 0/256 | 23:22 |
| mikek_VA3TEC | addr errors: 0/8192 | 23:22 |
| mikek_VA3TEC | data errors: 4/8388608 | 23:22 |
| mikek_VA3TEC | Memtest KO | 23:22 |
| mikek_VA3TEC | litex> | 23:22 |
| mikek_VA3TEC | litex> mem_speed 0x40000000 0x2000000 | 23:22 |
| mikek_VA3TEC | Memspeed at 0x40000000 (Sequential, 32.0MiB)... | 23:22 |
| mikek_VA3TEC | Write speed: 17.5MiB/s | 23:22 |
| mikek_VA3TEC | Read speed: 26.0MiB/s | 23:22 |
| mikek_VA3TEC | litex> | 23:22 |
| mikek_VA3TEC | litex> mem_speed 0x40000000 0x2000000 | 23:22 |
| mikek_VA3TEC | Memspeed at 0x40000000 (Sequential, 32.0MiB)... | 23:22 |
| mikek_VA3TEC | Write speed: 17.5MiB/s | 23:22 |
| mikek_VA3TEC | Read speed: 26.0MiB/s | 23:22 |
| mikek_VA3TEC | OK sorry.. | 23:22 |
| mikek_VA3TEC | I should use Pastebin then? | 23:22 |
| tpw_rules | that's fine by me | 23:23 |
| mikek_VA3TEC | how can I check that's it's 50Mt/s? | 23:23 |
| tpw_rules | it should say so when litex starts in the header | 23:23 |
| mikek_VA3TEC | I am still struggling with getting a Linux application working.. | 23:24 |
| mikek_VA3TEC | ok let me check. | 23:24 |
| tpw_rules | you can just use the reboot command to get it to print out again | 23:24 |
| mikek_VA3TEC | SDRAM:65536KiB 16-bit @ 50MT/s (CL-2 CWL-2) | 23:25 |
| mikek_VA3TEC | yup | 23:25 |
| mikek_VA3TEC | no long posts... :) | 23:25 |
| tpw_rules | so there is some overhead but theoretically you should get nearly 100MiB/s | 23:25 |
| mikek_VA3TEC | how do I do that? Sorry still learning here.. | 23:25 |
| tpw_rules | i don't know. it's a thing i've observed in litex in general. i just wondered if the channel knew the naser | 23:26 |
| tpw_rules | answer* | 23:26 |
| mikek_VA3TEC | I found this in the Init.. | 23:26 |
| mikek_VA3TEC | Memspeed at 0x40000000 (Sequential, 2.0MiB)... | 23:26 |
| mikek_VA3TEC | Write speed: 15.5MiB/s | 23:26 |
| mikek_VA3TEC | Read speed: 22.1MiB/s | 23:26 |
| tpw_rules | yes, it does a quick speed test during init to make sure the training worked (if necessary for your particular memory type) | 23:27 |
| mikek_VA3TEC | this is external hardware SDRAM so i would imagine that it's BW limited.. | 23:27 |
| tpw_rules | that's not really a factor | 23:27 |
| mikek_VA3TEC | I hear there is a calibration routine... where can I find that? | 23:27 |
| leons | So the Speedtest results presented there are a software Speedtest | 23:28 |
| leons | You need to build LiteDRAM with BIST enabled to have a hardware speedtest available as a command in the BIOS shell | 23:29 |
| mikek_VA3TEC | ok | 23:29 |
| leons | https://libera.irclog.whitequark.org/litex/2021-07-23#30329872; | 23:30 |
| tpb | Title: #litex on 2021-07-23 — irc logs at libera.irclog.whitequark.org (at libera.irclog.whitequark.org) | 23:30 |
| mikek_VA3TEC | is LiteDRAM separate from litex-boards? | 23:30 |
| mikek_VA3TEC | Thanks! | 23:31 |
| leons | Yes, all modules are split into different repositories. LiteX just contains the basic infrastructure and code to glue things together along with CPUs and basic peripherals, litex-boards is essentially a collection of SoC instantiations fit for a selection of different boards, with appropriate constraints | 23:33 |
| mikek_VA3TEC | Any Document ion on how to build LiteDRAM and then accessing it with litex-boards? I will start by looking at LiteDRAM. | 23:35 |
| tpw_rules | sdram does not have a calibration routine | 23:37 |
| mikek_VA3TEC | ok | 23:37 |
| tpw_rules | leons: hi? | 23:37 |
| tpw_rules | thank you for that link | 23:41 |
| tpw_rules | i didn't think the vexriscv would be that slow with cache but i guess we will find out | 23:41 |
| mikek_VA3TEC | Ah ok, I found where it has the SDram hardware.. sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}[mister_sdram] | 23:46 |
| mikek_VA3TEC | Line 129... | 23:46 |
| mikek_VA3TEC | But mine is version 2.5 have to get the microscope out to read the chips.. :) | 23:47 |
| mikek_VA3TEC | no long posts... :) | 23:47 |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!