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| tpw_rules | looks like some ram inference on broken | 01:19 |
|---|---|---|
| tpw_rules | is broken on cyclone v | 01:19 |
| tpw_rules | specifically for the linux soc. | 01:21 |
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| somlo | gatecat: thanks for pointing out flow3 -- I can get it to pass timing fairly comfortably at 50MHz (rocket on ecpix5) -- I created https://github.com/enjoy-digital/litex/pull/1435 | 12:33 |
| somlo | that said, it still fails dram initialization. Which is a strange coincidence, because `fulld` (128-bit wide memory bus with fpu) also fails dram initialization on the nexys_video (different board, different toolchain, same cpu verilog) | 12:35 |
| somlo | which makes me wonder if there's something broken about just the verilog for that particular variant (other variants of the same width work fine on both boards -- I can try more cores or drop the fpu and it's fine on nexys_video; I can only drop the fpu on ecpix5, but that's fine too :) ) | 12:36 |
| somlo | maybe https://github.com/enjoy-digital/litex/issues/1432 is caused by something wrong with that rocket variant rather than LiteDRAM? | 12:37 |
| somlo | the plot thickens... :) | 12:37 |
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| tpw_rules | i had some dram init failures when fooling around yesterday on cyclone v and was able to fix it by tweaking the clock phase. but my ram is boring old sdram | 14:06 |
| tpw_rules | https://github.com/litex-hub/litex-boards/blob/45494f60e0b9a996b2eeb1120f2ff634d580a6e8/litex_boards/targets/terasic_de0nano.py#L52 | 14:08 |
| tpw_rules | that same fix and comment is present on a lot of boards | 14:09 |
| somlo | this is litedram failing to "train" (read/write leveling) when the SoC is built with a very specific variant of rocket cpu (fpu-enabled, 128-bit wide memory port, single-core) | 16:09 |
| somlo | any other cpu of the same family (4-core, or single-core without fpu), same memory port width, works just fine | 16:10 |
| somlo | I'd prefer to find a way to tweak LiteDRAM or the leveling software initialization if possible -- digging into how the cpu is different from its brethren is *hard* (requires understanding Chisel :)) | 16:10 |
| somlo | so I'd prefer to do that only if nothing else works first :D | 16:11 |
| tpw_rules | it seems quartus is unable to infer Migen RAMs | 17:24 |
| tpw_rules | sometimes | 17:28 |
| tpw_rules | is there a way to like increase the verbosity? | 17:39 |
| tpw_rules | when quartus doesn't infer it it doesn't even mention it | 17:39 |
| tpw_rules | oh, it's dependent on the size. amazing | 17:54 |
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