| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 248 seconds) | 02:18 | |
| *** Degi <[email protected]> has joined #litex | 02:19 | |
| *** cr1901_ <cr1901_!~cr1901@2601:8d:8600:911:1035:c18c:19bd:b286> has joined #litex | 03:06 | |
| *** cr1901 <cr1901!~cr1901@2601:8d:8600:911:3068:cb2c:1b9:b0b1> has quit IRC (Ping timeout: 264 seconds) | 03:10 | |
| *** cr1901_ is now known as cr1901 | 05:20 | |
| cr1901 | _florent_: When you're around, would you be willing to explain the comment on this line here about the PLL phase? https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/trenz_tec0117.py#L100 | 05:20 |
|---|---|---|
| pepijndevos[m] | What options are there on an ice40 to run litex when the bitstream is loaded in spi slave mode by an esp32? https://www.bodge.team/docs/badges/mch2022/ | 12:16 |
| tpb | Title: MCH2022 badge | BADGE.TEAM (at www.bodge.team) | 12:16 |
| tnt | IMHO is a custom bootloader and wrap the ESP<->iCE40 comm stuff we have made as a wishbone peripheral for your SoC. | 13:15 |
| *** rtypo_bot <rtypo_bot!~rtypo_bot@user/rtypo-bot/x-3951806> has joined #litex | 15:09 | |
| *** rtypo_bot <rtypo_bot!~rtypo_bot@user/rtypo-bot/x-3951806> has left #litex | 15:09 | |
| *** shorne <[email protected]> has quit IRC (Remote host closed the connection) | 20:53 | |
| *** shorne <[email protected]> has joined #litex | 20:57 | |
| jevinskie[m] | Ok, I got the pads/signals all hooked up with VPI. Now I need to turn the event loop inside out or… | 22:03 |
| jevinskie[m] | something… since verilator’s event loop is driven by the c++ harness and vpi just gives me callbacks | 22:03 |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!