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| cr1901 | pepijndevos[m]: This might be a silly q, and I'm sorry if it is, but... what's the context of needing a phase shift here: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/trenz_tec0117.py#L100 | 01:00 |
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| jevinskie[m] | OK, halfway done with the icarus verilog support. Now I need to add the VPI<>Verilator shim magic, which I can at least reuse for questa as well. https://github.com/enjoy-digital/litex/compare/5240bf04bec27aca293699c053b8e1c070a1d238...jevinskie:litex:jev/usbstream-usbbone/main | 03:43 |
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| pepijndevos[m] | <cr1901> "pepijndevos: This might be a..." <- I uh have no idea | 05:28 |
| cr1901 | pepijndevos[m]: Your name is at the top of the file, so I thought you might know :P | 05:30 |
| cr1901 | Oh, oops... blame says _florent_ added that line | 05:30 |
| cr1901 | My mistake | 05:30 |
| pepijndevos[m] | Yea i started it but didn't do the pll part | 05:42 |
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| jevinskie[m] | Ok, finally figured out baby’s first VPI module. Strangely I couldn’t find a “hello world” vpi example that just dumps a signal when it changes. https://github.com/jevinskie/litex-alternative-sims/blob/main/serial2tcp_bare/serial2tcp.c | 18:36 |
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