Wednesday, 2022-05-18

*** tpb <[email protected]> has joined #litex00:00
*** peeps[zen] <peeps[zen]!~peepsalot@openscad/peepsalot> has quit IRC (Quit: Connection reset by peep)01:18
*** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has joined #litex01:21
*** Degi_ <[email protected]> has joined #litex03:49
*** Degi <[email protected]> has quit IRC (Ping timeout: 272 seconds)03:49
*** Degi_ is now known as Degi03:49
*** cr1901_ <cr1901_!~cr1901@2601:8d:8600:911:583d:eb3c:f0d4:2fa2> has joined #litex05:28
*** cr1901 <cr1901!~cr1901@2601:8d:8600:911:507a:a18b:6a75:4106> has quit IRC (Ping timeout: 240 seconds)05:31
*** cr1901_ is now known as cr190105:58
*** acathla_ <[email protected]> has joined #litex05:59
*** acathla <[email protected]> has quit IRC (Ping timeout: 246 seconds)06:00
*** mlaga97 <mlaga97!~quassel@user/mlaga97> has quit IRC (Ping timeout: 246 seconds)06:01
*** mlaga97 <mlaga97!~quassel@user/mlaga97> has joined #litex06:01
tntMmm, AFAICT there is no way in migen to generate the `ramstyle=”ultra”` needed on a Memory to get the tool to infer ultra ram blocks.06:54
*** FabM <[email protected]> has joined #litex06:57
_florent_tnt: I'll do a test with 512-bit on the XCU1525 design07:20
_florent_tnt: The verilog/memory generation is now directly integrated in LiteX; I haven't tried to used UltraRAM yet with LiteX. Can you share some expected verilog code to infer them? I could try to add this07:22
*** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.)07:23
*** TMM_ <[email protected]> has joined #litex07:23
*** davebee <[email protected]> has joined #litex07:54
*** Guest1751 <Guest1751!~Guest1751@host109-147-65-10.range109-147.btcentralplus.com> has joined #litex08:12
*** cr1901_ <cr1901_!~cr1901@2601:8d:8600:911:d1f0:2e29:5946:9ad0> has joined #litex12:08
*** cr1901 <cr1901!~cr1901@2601:8d:8600:911:583d:eb3c:f0d4:2fa2> has quit IRC (Ping timeout: 240 seconds)12:11
*** cr1901 <cr1901!~cr1901@2601:8d:8600:911:ca4:8e3e:7dba:8c54> has joined #litex12:12
*** cr1901_ <cr1901_!~cr1901@2601:8d:8600:911:d1f0:2e29:5946:9ad0> has quit IRC (Ping timeout: 240 seconds)12:15
*** genpaku <[email protected]> has quit IRC (Ping timeout: 276 seconds)13:25
*** rektide <[email protected]> has quit IRC (Remote host closed the connection)13:28
*** genpaku <[email protected]> has joined #litex13:32
*** rektide <[email protected]> has joined #litex13:33
*** davebee <[email protected]> has quit IRC (Quit: Leaving)13:54
*** davebee <[email protected]> has joined #litex13:54
*** rektide <[email protected]> has quit IRC (Ping timeout: 272 seconds)13:54
*** rektide <[email protected]> has joined #litex14:00
*** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Quit: Leaving)14:48
*** davebee <[email protected]> has quit IRC (Quit: Leaving)15:59
_florent_somlo: I just added IRQ/Identify support to LiteSATA gateware and the BIOS is now running the Identify command during SATA init to get disk information16:07
_florent_somlo: https://github.com/enjoy-digital/litex/commit/1d20bbcd01784158088e1eb85e219309cfce024816:07
somlo_florent_: awesome, I'm building it right now and will test it as soon as it's finished 16:15
somloI'll be traveling starting tomorrow until Monday, so no opportunity to tinker with the linux driver, but I should hopefully have some time to add write, irq, and identify (really just set the device size) support sometime starting next week16:16
somlooh and partition detection when the device is successfully probed -- seems to be another layer on top of just having a raw block/disk :)16:17
_florent_somlo: no hurry, I just wanted to implement it to avoid blocking you (and to remove it from my todo list :))16:20
somloI saw the work you did earlier (before the bios identify example) and had already started building it, with the intention of studying the identify python stuff in litesata later on16:24
somloso it's nice to have a "color by numbers" example already implemented, saves me from having to learn *too* many new things ;)16:25
pepijndevos[m]hmmm so how do I synthesize VHDL with Litex? It tries to use yosys with read_vhdl. Does that require verific? Can I make it use GHDL?18:05
pepijndevos[m]pffffff https://github.com/enjoy-digital/litex/blob/1d20bbcd01784158088e1eb85e219309cfce0248/litex/soc/cores/cpu/microwatt/core.py#L218-L23218:15
*** Guest1751 <Guest1751!~Guest1751@host109-147-65-10.range109-147.btcentralplus.com> has quit IRC (Quit: Client closed)19:42
*** benh <[email protected]> has quit IRC (Remote host closed the connection)22:30
*** benh <[email protected]> has joined #litex22:31
*** Guest32 <[email protected]> has joined #litex23:44
*** Guest32 is now known as Albert23:47
*** Albert is now known as Guest842123:48

Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!