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| _florent_ | swetland: might be of interest: https://twitter.com/enjoy_digital/status/1403259359518396418 | 04:48 |
|---|---|---|
| _florent_ | https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-824602314 | 04:48 |
| _florent_ | https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-859366899 | 04:49 |
| _florent_ | the modification is really easy to do | 04:49 |
| swetland | florent: I actually have a couple of those around somewhere. Also I'm having JLCPCB fab me a few of these: https://twitter.com/dnaltews/status/1526225492583403523 | 05:12 |
| swetland | thanks for the pointers! | 05:14 |
| swetland | perhaps unsurprisingly mine already is modified: http://frotz.net/misc/phy-module.jpg | 05:21 |
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| pepijndevos[m] | is ResetSignal active high? https://m-labs.hk/migen/manual/reference.html#migen.fhdl.structure.ResetSignal | 10:59 |
| tpb | Title: API reference — Migen 0.8.dev0 documentation (at m-labs.hk) | 10:59 |
| tnt | yes | 11:00 |
| pepijndevos[m] | ty | 11:08 |
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| tnt | _florent_: Can I just set data_width to 512 to the PCIe PHY ? Or does it need other changes ? | 20:02 |
| tnt | Because turns out with sys_clk of 200 MHz, 256b is "only" 51.2Gb/s (vs 64 Gb/s theoritical) | 20:03 |
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| _florent_ | tnt: this should do it yes, I just checked the xcu1525 bench and data_width is only passed to the PHY | 20:42 |
| _florent_ | https://github.com/enjoy-digital/litepcie/blob/master/bench/xcu1525.py#L69 | 20:42 |
| tnt | _florent_: definitely doesn't work :) Crashes the host for me. | 21:10 |
| tnt | (on modprobe) | 21:10 |
| jevinskie[m] | _florent_: I’ve looked at the 7 series PHYs in litedram and when looking to port to max10 I realized they only have dedicated serdes on the lvds bank not the ram banks. Guess I’ll have to implement that in logic? | 21:48 |
| jevinskie[m] | And I think the max10 programmable delays are fairly limited in range/precision and are fixed at synthesis time | 21:53 |
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