Tuesday, 2022-05-17

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_florent_swetland: might be of interest: https://twitter.com/enjoy_digital/status/140325935951839641804:48
_florent_the modification is really easy to do04:49
swetlandflorent: I actually have a couple of those around somewhere.  Also I'm having JLCPCB fab me a few of these: https://twitter.com/dnaltews/status/152622549258340352305:12
swetlandthanks for the pointers!05:14
swetlandperhaps unsurprisingly mine already is modified: http://frotz.net/misc/phy-module.jpg05:21
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pepijndevos[m]is ResetSignal active high? https://m-labs.hk/migen/manual/reference.html#migen.fhdl.structure.ResetSignal10:59
tpbTitle: API reference — Migen 0.8.dev0 documentation (at m-labs.hk)10:59
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tnt_florent_: Can I just set data_width to 512 to the PCIe PHY ?  Or does it need other changes ?20:02
tntBecause turns out with sys_clk of 200 MHz, 256b is "only" 51.2Gb/s (vs 64 Gb/s theoritical)20:03
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_florent_tnt: this should do it yes, I just checked the xcu1525 bench and data_width is only passed to the PHY20:42
tnt_florent_: definitely doesn't work :)  Crashes the host for me.21:10
tnt(on modprobe)21:10
jevinskie[m]_florent_: I’ve looked at the 7 series PHYs in litedram and when looking to port to max10 I realized they only have dedicated serdes on the lvds bank not the ram banks. Guess I’ll have to implement that in logic?21:48
jevinskie[m]And I think the max10 programmable delays are fairly limited in range/precision and are fixed at synthesis time21:53
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