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| somlo | _florent_: updated the litesata driver in the `litex-rebase` kernel branch: uses `ident` to determine size, and detects partitions. No write support yet, and mounting partitions fails (either b/c of unsupported writes, or more likely I have some sort of stride error when I read sectors within a bvec or something). I'll figure it out next week :) | 01:07 |
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| jevinskie[m] | Anybody have recommendations for adapting litedram PHY for use on max10 that doesn’t have any serdes primitives on the external memory bank IOEs? They only have plain DDR registers. Should I just write the serdes in fpga logic? I guess that’s what the altera IP must do, I just wonder if it will be fast enough. Xilinx SelectIO is pretty spiffy compared to the more basic intel parts… | 03:11 |
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| cr1901 | _florent_: Just to be clear: litevideo and opentitan are no longer used/supported, so I can safely delete those repos from my disk? | 04:10 |
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| swetland | _florent_: can't quite figure out how to wire up the clocks | 06:26 |
| swetland | Exception: Unresolved clock domain eth, availables: sys sys_ps hdmi hdmi5x eth_rx eth_tx | 06:27 |
| swetland | these migen ? errors resulting in big spews of python backtrace are unfun to try to unravel | 06:28 |
| swetland | okay... kosagi_netv2 had an approach that at least is getting things to build, though I'm a bit unclear on what direction liteeth is expecting ref_clk to be in | 06:35 |
| _florent_ | swetland: can you share your target file? I could have a quick look | 06:53 |
| swetland | I got it sorted. muselabs board is exchanging packets with my workstation now | 06:58 |
| swetland | arp is working and then it tries to hit tftp. so it appears to be hearing the responses as well | 06:59 |
| _florent_ | ok good | 07:09 |
| swetland | I do need to figure out how to set it up to handle driving refclk *to* the phy instead of accepting it from the phy once my boards get back from jlcpcb | 07:10 |
| swetland | am I right in my assumption that the only documentation on how to use liteeth from a sw perspective is the source code for the bios? | 07:12 |
| _florent_ | that's right yes, source of the bios or of the linux driver: https://github.com/torvalds/linux/blob/ca2ef2d9f2aad7a28d346522bb4c473a0aa05249/drivers/net/ethernet/litex/litex_liteeth.c | 07:15 |
| swetland | cool. just wanted to be sure I wasn't missing some human readable docs somewhere. (it doesn' | 07:17 |
| swetland | t look like a terribly complicated interface) | 07:17 |
| swetland | I have to say, it's quite impressive how much stuff Just Works most of the time with Litex. | 07:32 |
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| betocool | Hi all, I'm new to Litex here. Yet to start tinkering with Litex-Migen, either on a Nano board or an Arty A7. I find the concept very interesting. | 08:05 |
| pepijndevos[m] | would it be possible to teach litex to use ghdl for synthesis of vhdl? That microwatt hack of manually compiling to verilog seems somewhat... unfortunate | 08:06 |
| betocool | Question out of curiosity, would it be able to use LiteEth with LWiP on a baremetal uC (Risc-V) or as a FreeRTOS add on? | 08:06 |
| gatecat | betocool: see no reason why not - I believe there's already Zephyr support for liteeth which might be useful for inspiration | 08:10 |
| shenki | we also have a u-boot liteeth. lots of examples to follow. | 08:20 |
| betocool | shenki: That will be interesting to see... Of all Litex projects, which one should I start to unravel to get a better idea of all interconnects, cpus, cores, etc? | 08:40 |
| betocool | Oh, also... I'm assuming this is the right place to ask beginner questions? | 08:41 |
| _florent_ | Playing a bit with CoreScore on a VU19P :) : https://twitter.com/enjoy_digital/status/1527205528098721792 | 08:48 |
| _florent_ | pepijndevos[m]: we should indeed automates the use of GHDL for toolchain not supporting VHDL | 08:49 |
| _florent_ | betocool: at some point we were using LWiP with LiteEth: https://github.com/enjoy-digital/liteeth/commit/0688532619fd2b111990066c8afce9132935afb9 | 08:51 |
| _florent_ | betocool: this should still work | 08:51 |
| pepijndevos[m] | at the moment GHDL can't correctly synth my design so maybe I'll just give up on the idea and write it in Migen :( | 08:51 |
| _florent_ | pepijndevos[m]: ah strange, are you using un-common VHDL design patterns? I've been using GHDL synth to prototype design in LiteX/Migen and progressively switch to VHDL and had that much issues with GHDL synth. | 08:54 |
| pepijndevos[m] | I think it's choking on using the `abs` function | 08:55 |
| _florent_ | betocool: Documentation in the project is still limited, but you to have a better overview of the project, you can have a look at the wiki: https://github.com/enjoy-digital/litex/wiki | 08:56 |
| _florent_ | betocool: and the Tutorial/Resources: https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources | 08:57 |
| pepijndevos[m] | so far it looks like using ghdl to generate verilog directly is more reliable than using yosys... and also simpler to install and manage | 09:07 |
| _florent_ | ok, interesting, I think I only tested the VHDL -> GHDL-Synth -> Yosys -> Verilog flow | 09:13 |
| pepijndevos[m] | yea I tried that initially, and that used to be the only path | 09:17 |
| pepijndevos[m] | But turns out these days you can do `ghdl --synth --out=verilog` and bypass yosys if all you need is verilog code | 09:18 |
| pepijndevos[m] | uhh... how can I make a `Signal(4)` out of some pins in a connector? https://github.com/litex-hub/litex-boards/blob/64773b40850dfb94aae1ab82e1169c5a449435a0/litex_boards/platforms/colorlight_5a_75b.py#L296 | 09:19 |
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| _florent_ | with something like this: https://github.com/enjoy-digital/litesdcard/blob/master/bench/arty.py#L55-L63 | 09:24 |
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| pepijndevos[m] | so `("H1", 0, Pins("j1:0 j1:1 j1:2 j1:3"), IOStandard("LVCMOS33"))` would take pins out of the j1 connector I supposed | 09:36 |
| pepijndevos[m] | it's compiling!!! | 09:40 |
| pepijndevos[m] | <_florent_> "litex_server --udp" <- hmmmm I already forgot how I did it last time but now I get `AttributeError: 'RemoteClient' object has no attribute 'regs'` | 11:24 |
| tnt | you need the csr.csv file | 11:28 |
| pepijndevos[m] | yea that seems to be it... | 11:31 |
| pepijndevos[m] | now it's doing reeeeeally weird things | 11:39 |
| pepijndevos[m] | it sorta boots but then times out and spams a looot of whitespace and then resets a few times and then has an error in the etherbone stuff or something | 11:39 |
| trabucayre | comment tu m'as trouvé sur mastodon toi? | 12:12 |
| pepijndevos[m] | oui (wait no I can understand this, don't spoil it) | 12:18 |
| pepijndevos[m] | how you can find me on mastodon? | 12:19 |
| trabucayre | oups... wrong chan :-/ | 12:19 |
| pepijndevos[m] | I figured ;) | 12:20 |
| trabucayre | => how did you find me on mastodon you :) | 12:20 |
| pepijndevos[m] | ah close... yea I wasn't sure about the m'as and toi parts the rest seemed... familiar | 12:21 |
| trabucayre | I have closed one window -> lost my habits :) | 12:21 |
| pepijndevos[m] | hmmmm so I've managed to get UART working without the etherbone stuff and it's stable now, but now I don't have a blinky and reset button any more. | 12:23 |
| _florent_ | Practice your french in #litex channel with trabucayre; lesson one May 19: How to kindly ask how your friend how (s)he found your mastodon account with the french attitude :) | 12:29 |
| _florent_ | pepijndevos[m]: IIRC correctly Etherbone was working correctly for you on Colorlight a few days ago no? Are you using a different configuration? | 12:31 |
| pepijndevos[m] | yea it was working before... only difference should be that I've added my own IP | 12:31 |
| pepijndevos[m] | but it's fine to use serial UART, makes it easier to experiment with the Ethernet probably. | 12:32 |
| pepijndevos[m] | Only problem is now I'm not sure how to reset the device to upload new software. | 12:33 |
| trabucayre | _florent_: :-/ | 12:33 |
| pepijndevos[m] | I guess powercycle it... | 12:33 |
| pepijndevos[m] | or is there a way to make the software reset itself? Like... jump to litex | 12:33 |
| trabucayre | its really it's perfectly kindly on the contrary :) | 12:34 |
| pepijndevos[m] | hmmm actually yea I could just jump to the bios address maybe? | 12:34 |
| pepijndevos[m] | I kinda want to learn french... It's like... I know just enough to be dangerous but no grammar at all | 12:35 |
| _florent_ | trabucayre: hehe | 12:35 |
| _florent_ | pepijndevos[m]: are you aware of this BTW: https://twitter.com/Claude1079/status/1231194849350647808, could be useful to modify at least one connector to have more In/Out IOs | 12:36 |
| pepijndevos[m] | yea I've seen it | 12:38 |
| pepijndevos[m] | also someone made a flexpcb mod that just wired them straight through | 12:38 |
| _florent_ | pepijndevos[m]: on thing you can also but, but not sure how fast it will be: | 12:38 |
| pepijndevos[m] | for now I can get away with only outputs, mostly... | 12:38 |
| _florent_ | instead or regular UART, use UARBone + Crossover UART | 12:39 |
| _florent_ | 2s, I'll give you the commands | 12:39 |
| _florent_ | so build with --uart-name=crossover+uartbone | 12:40 |
| _florent_ | then open litex_server with --uart --uart-port=/dev/ttyUSBX | 12:40 |
| _florent_ | then litex_term crossover | 12:41 |
| _florent_ | this should allow you to load/execute your firmware as you were doing over etherbone | 12:41 |
| _florent_ | and you can also open litex_cli --gui in parallel | 12:42 |
| _florent_ | which will allow you to write/read the register of the SoC | 12:42 |
| _florent_ | registers | 12:42 |
| _florent_ | and should also have a reboot button | 12:42 |
| pepijndevos[m] | wait I'm confused... | 12:43 |
| pepijndevos[m] | what does --uart-name=crossover+uartbone actually do? | 12:43 |
| pepijndevos[m] | Before I had crossover, and etherbone, and that somehow allowed me to use wishbone over ethernet. Now I have serial, which allows me to connect over UART, but uses the same pins as the LED/BTN | 12:44 |
| _florent_ | yes, so with crossover+uartbone, you are going to replace etherbone with uartbone and will still use the crossover uart | 12:45 |
| _florent_ | so the UART is tunneled over the UARTBone | 12:46 |
| _florent_ | you'll get something similar to this: | 12:47 |
| _florent_ | https://twitter.com/enjoy_digital/status/1503799370877403136 | 12:47 |
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| shenki | _florent_: why did you stop at 6000? :) | 12:47 |
| _florent_ | pepijndevos[m]: basically, you are deporting the reboot button to your Host :) | 12:48 |
| _florent_ | pepijndevos[m]: what's also funny is that there is continous refresh of the registers, so you see the SoC behaving through the CSR registers | 12:49 |
| pepijndevos[m] | ohhhhhh | 12:49 |
| _florent_ | pepijndevos[m]: like this: https://twitter.com/enjoy_digital/status/1509476885641711621 | 12:49 |
| pepijndevos[m] | so litex_cli --gui is what has the reset button? | 12:50 |
| _florent_ | yes, and litex_term/litex_cli will both be connected to litex_server that will share access to the hardware | 12:51 |
| pepijndevos[m] | and I guess this also allows me to poke the registers of my peripheral which is neat | 12:51 |
| _florent_ | the interface is very simple for now, but has already been useful for such things yes | 12:52 |
| pepijndevos[m] | awesome | 12:52 |
| pepijndevos[m] | trabucayre: quand est la prochaine leçon | 12:53 |
| _florent_ | shenki: that was just a first test, just wanted to see how the vu19P would be filled with the previous top CoreScore on VU37P (but still beat it by +1 :)) | 12:56 |
| _florent_ | shenki: another version is running | 12:57 |
| shenki | nice | 12:57 |
| shenki | _florent_: how long did the first run take? | 12:57 |
| _florent_ | shenki: not that long in fact, 13H and not on a particularly optimized setup: I7/7700K with Windows 10 and Vivado running in a Ubuntu 20.04 VM... | 13:00 |
| _florent_ | shenki: you just need to put enough RAM in the machine to avoid a Vivado crash... | 13:00 |
| shenki | Ahh, what would sythesis be without a Vivado crash | 13:01 |
| shenki | very cool. What's your prediction for the maximum corescore? | 13:02 |
| _florent_ | probably between 15000-18000, but not sure how long it will take on this machine with the congestions. | 13:03 |
| _florent_ | shenki: in fact a more useful experiment with these big FPGAs (at least for LiteX), would be to create a LiteX design with SoC peripherals in common and all the supported CPU softcores implemented in the same design and that could be selected as the main CPU of the SoC. Would be nice for CPU regression tests: One board, one bitstream to verify all the CPUs (and also eventually verify the Linux boot on the ones supporting it). | 13:08 |
| _florent_ | the VU19P is from a client but I have some VU9P (recycled from mining) that I could use for this. | 13:10 |
| pepijndevos[m] | _florent_: yeeaaahhh so the uartbone gives a similar problem where it seems there is a timeout error between the terminal and the litex_server | 13:16 |
| pepijndevos[m] | The GUI gives the same timeout | 13:16 |
| shenki | _florent_: that would be a fun experiment. A sure way to flush out some bugs in litex | 13:18 |
| trabucayre | pepijndevos[m]: next time I close an IRC window :) | 14:07 |
| pepijndevos[m] | deal | 14:08 |
| pepijndevos[m] | bleg | 14:19 |
| pepijndevos[m] | The gui is actually great for poking registers but I can't seem to upload my code with this config: `[LITEX-TERM] Got unexpected response from device 'b';''` | 14:20 |
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| _florent_ | pepijndevos[m]: can you try to add --safe to litex_term? (I think that what I also suggested when you were using Etherbone) | 16:11 |
| pepijndevos[m] | what does that do? | 16:12 |
| pepijndevos[m] | At the moment I'm just calling reset at the end of my program, so I can upload it, and as long as I keep the terminal open it'll keep uploading it, but if I close it it just goes back to the bios. Works well enough for now. | 16:13 |
| pepijndevos[m] | hm maybe --safe will fix the upload issue, but it'll not fix the timeout, which seems to be a problem with the litex_server since both the GUI and the terminal have the same timeout after a while. | 16:15 |
| _florent_ | this force litex_term to wait for the CPU ack before transmiting the next packet. So is slow since you pay the round-trip latency for each packet but should work in all cases. | 16:16 |
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| jevinskie[m] | _florent_: I see that the lpddr4 PHY uses utils Serializer/Deserializer to make a 16:1 serdes from 8:1 HW serdes. I guess I should try using it as an 8:1 serdes for the max10 IOE? | 19:21 |
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| swetland | okay, wacky... litex *does* provide the clock to the 8720A module by default... I had assumed since the module had a 50M oscillator it was configured the other way around | 20:40 |
| swetland | what's the simplest way to talk to something over etherbone? (is there a trivial little tool to just read/write memory/registers?) | 21:24 |
| sajattack[m] | I think wishbone_tool or something | 21:42 |
| sajattack[m] | Can't remember the exact names | 21:42 |
| sajattack[m] | wishbone_tool and litex_cli maybe | 21:42 |
| sajattack[m] | swetland: | 21:43 |
| jevinskie[m] | swetland: RemoteClient python class could be used from a Python REPL or simple script. Here is a more complicated script that does bitfield decoding but it illustrates the use of RemoteClient | 21:57 |
| jevinskie[m] | https://github.com/jevinskie/liteeth/blob/jev/altera-gmii/liteeth/software/liteeth_mdio.py | 21:57 |
| swetland | looks like litex_server talks to wishbone and then other tools talk to it? | 22:10 |
| swetland | er etherbone | 22:10 |
| sajattack[m] | https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC | 22:10 |
| jevinskie[m] | yep. i forget if wishbone_tool talks directly to the fpga or not | 22:10 |
| swetland | is etherbone a stable protocol? is there a spec somewhere? | 22:14 |
| swetland | https://ohwr.org/project/etherbone-core/wikis/Documents/Etherbone-full-specifications dates to 2012 | 22:15 |
| tpb | Title: Etherbone full specifications · Wiki · Projects / EtherBone Core · Open Hardware Repository (at ohwr.org) | 22:15 |
| jevinskie[m] | https://accelconf.web.cern.ch/icalepcs2011/papers/webhmult03.pdf | 22:16 |
| jevinskie[m] | check out the last page | 22:16 |
| swetland | hm. memory reads seem to return 0 or timeout. but it does seem to be interacting with the board | 22:29 |
| jevinskie[m] | I'd try checking using a different transport (eth/jtag/uart) | 22:30 |
| * swetland nods | 22:30 | |
| swetland | writing a little test program it seems like a very large percentage of rx packets have crc errors | 23:51 |
| swetland | wondering if there's a clock alignment issue | 23:51 |
| swetland | the cheesy trick of swapping 0 and 1 here fixes rx for me: self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx")) | 23:56 |
| swetland | (liteeth/phy/rmii.py) | 23:56 |
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