Sunday, 2022-05-15

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xobs[m]I think one of the things that I don't like about RISC-V is that it has 32 general-purpose registers, meaning a context switch is surprisingly heavy. It's 64 cycles at a minimum (32 pushes followed by 32 pops). Occasionally I find myself thinking register windows were a good idea.00:17
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xobs[m](Then I come to my senses, of course.)00:19
swetlandyeah.  even interrupts require saving at least 16 registers on the way in.  On the other hand at 50MHz, 64 cycles is only 1.28uS so that's survivable01:10
tpw_rulesdoes it not have an interrupt register bank?01:13
swetlandnope.  there are 32 general registers (one is always 0) and a pc01:39
swetlandthere is a single scratch machine register that you can use to assist in shuffling stuff around on irq or exception01:39
swetlandtypically you point it at a kernel stack or thread struct or the like and you swap sp with that, then stow the caller-save registers so they're not corrupted, then call into your irq/exception code01:40
swetlandxobs[m]: my least favorite thing about RISCV is the SBI01:41
swetlandI really really dislike enshrining a (potentially blackbox) machine monitor (like intel SMI) to handle activities that really should be handled by the OS in supervisor mode01:42
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xobs[m]Even more if you've got floating point02:49
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pepijndevos[m]Are there any examples for making a peripheral in vhdl? I found on the wiki how to add vhdl instances, but I mean more... How to expose a register that a core can read/write08:07
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_florent_pepijndevos[m]: you just need to create a mmap peripheral with Wishbone, AXI or AXI-Lite interface and connect it like this:17:31
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_florent_Sorry not sure I have open-source examples to share directly with LiteX, but you could follow any mmap open source core, you'll probably find more Wishbone examples17:32
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pepijndevos[m]Hmm so you'd need to implement a wishbone thing in vhdl... Something I imagine is built in with litex. Maybe I could just do that part in litex and just have that as a stdlogicvector into vhdl? 17:56
tntxobs[m]: I often end up using non-standard extension that "swap" register bank ...17:56
tntpepijndevos[m]: yeah, if all you need is a single register, going using a AutoCSR / CSR thing that creates the register and then just feed it as an input to the instance of you vhdl core seems the easiest.17:59
pepijndevos[m]I think I'll just riff on the pwm core18:04
pepijndevos[m]Honestly not sure it's even worth going down to VHDL. I want to do a stepper motor driver, which is honestly not much more complicated than PWM. It's just... migen is great for plumbing and metaprogramming but I don't like the syntax for actual logic18:46
_florent_pepijndevos[m]: I generally encourage developers to only use LiteX for use-cases they find useful for them, so in your case just doing the plumbing + using AutoCSR with CSR connected to input/output of the VHDL design as suggested tnt seems the best. 18:57
_florent_pepijndevos[m]: I'm also doing that a lot when re-integrating existing VHDL/Verilog cores and to prototype things with the plumbing in LiteX first and then write things in VHDL when the final architecture is found.18:59
pepijndevos[m]sounds good19:11
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Wolfvakhi, after trying the latest linux-on-vexriscv in my orangecrab 25f I find that the available memory is now 64MiB? did I misconfigure something on build or can someone replicate this?20:57
Wolfvakused "./ --board orangecrab --build --dcache-size 16384 --dcache-ways 4 --icache-size 16384 --icache-ways 4 --with-rvc --load" for building and flashing btw20:58
cr1901pepijndevos[m]: If you want your core to be decoupled from your SoC, you may consider something like pythondata-auto to "wrap" your VHDL:
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