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| sajattack[m] | Did the cle215 carrier board ever come to fruition? | 00:48 |
|---|---|---|
| zyp | maybe stuck on part availability like everything else? | 01:14 |
| sajattack[m] | probably :P | 01:58 |
| _florent_ | sajattack[m]: we still have to finish the validation of the ECP5 <-> Artix7 link and ECP5/Ethernet PHY are not available currently, so even if fully validated it would not be possible to produce it. | 06:40 |
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| pepijndevos[m] | welp I know too little about JTAG. Trying to program the colorlight board with some FT2232 thingy but not having much luck | 08:09 |
| tnt | pepijndevos[m]: openfpgaloader should handle pretty much all of it right ? | 08:10 |
| pepijndevos[m] | yea but I'm getting weird errors and I think it's maybe an electronic problem | 08:10 |
| pepijndevos[m] | I get inconsistent IDCODE readouts | 08:11 |
| pepijndevos[m] | JTAG init failed with: Unknown device with IDCODE: 0xe8244003 (manufacturer: 0x001 (), part: 0x41 vers: 0xe | 08:11 |
| tnt | what speed are you using ? | 08:12 |
| pepijndevos[m] | I tried --freq 1000 with little difference | 08:12 |
| pepijndevos[m] | one time it randomly worked. Most of the time it gets the manufacturer right... | 08:13 |
| tnt | you can try --invert-read-edge but if it doesn't work even at 1 MHz, not sure it would help | 08:14 |
| pepijndevos[m] | yea no change | 08:14 |
| pepijndevos[m] | $ openFPGALoader --cable ft2232 --freq 100 --invert-read-edge --detect | 08:14 |
| pepijndevos[m] | Jtag frequency : requested 100.00Hz -> real 100.00Hz | 08:14 |
| pepijndevos[m] | JTAG init failed with: Unknown device with IDCODE: 0xe0891043 (manufacturer: 0x021 (lattice), part: 0x04 vers: 0xe | 08:14 |
| pepijndevos[m] | and uh... JTAG is a clocked protocol yea? So it's not like UART where you can get garbage if the oscillators is running wrong or whatever | 08:15 |
| tnt | yes | 08:15 |
| pepijndevos[m] | and... if I have the wiring wrong it wouldn't work at all right... | 08:18 |
| tnt | heh ... that I'm not sure. | 08:18 |
| tnt | seems unlikely but maybe some random thing on tdi/tms would still read something on tdo | 08:19 |
| pepijndevos[m] | I have the Colorlight 5A-75B V8.0 and the way I have it hooked up now is that TCK/TMS/TDI/TDO go to the header, ground to the other header, and 5V to the main power input. So it gets 3.3v from there, not from the FTDI thing, which I've left disconnected. | 08:20 |
| pepijndevos[m] | I guess I'll double-check all the wires and maybe try giving it an external power supply | 08:20 |
| gatecat | 0xe8244003 still kinda looks a bit like an ecp5 idcode but shifted or a bit corrupted or something | 08:20 |
| tnt | does the fpga need to be held in reset ? Can't remember ... | 08:21 |
| pepijndevos[m] | yea, it reports that it's a latice device half of the time, which made me think it's like a slightly wrong frequency. | 08:21 |
| gatecat | could be something like a bad clock signal causing double clocking | 08:22 |
| gatecat | you could try like a 100r series resistor on tck, close to the ftdi | 08:22 |
| gatecat | I think I've also seen like 1k pulldown on tck used to try and prevent this | 08:22 |
| pepijndevos[m] | time to move it to the lab for some close inspection I guess | 08:23 |
| pepijndevos[m] | hmmmm TDO looks wonky when it's connected to the JTAG | 08:48 |
| * pepijndevos[m] uploaded an image: (48KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/UwmhYFtcwlPjCxUrCJjPQcWn/RigolDS0.png > | 08:50 | |
| * pepijndevos[m] uploaded an image: (48KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/ViHEgVRpRESUUqsHqDNexpkq/RigolDS1.png > | 08:50 | |
| pepijndevos[m] | There also shouldn't be any confusion over TDI/TDO like RX/TX right? | 08:53 |
| tnt | Depends how your jtag adapter is labelled ... | 08:54 |
| tnt | pin 18 should be connected to the FPGA TDO. | 08:55 |
| tnt | https://i.imgur.com/QbxuBXE.png | 08:56 |
| * pepijndevos[m] uploaded an image: (158KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/UUkdPVPLOxVOuLulIebSLAvI/IMG_20220429_105738.jpg > | 08:57 | |
| pepijndevos[m] | are any of these pins supposed to bidirectional? because there is some output on TDO when disconnected | 09:02 |
| tnt | no | 09:08 |
| * pepijndevos[m] uploaded an image: (52KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/hsbJlgklbHqOBDcQQYPKNjJP/RigolDS2.png > | 09:08 | |
| tnt | https://raw.githubusercontent.com/q3k/chubby75/master/5a-75b/jtag.jpg | 09:12 |
| tnt | Aren't you wired backward ? | 09:12 |
| pepijndevos[m] | > Note that the pinout below only works for V6.1 and V7.0 boards. V8.0 board has a different pinout, check the corresponding board page. | 09:27 |
| pepijndevos[m] | if I'm getting output on the TDO pin of the FTDI thing, that seems extremely wrong?? | 09:29 |
| tnt | well tbh, at the beginning it's not surprising because during init/config the ftdi tends to go random stuff since it's not _only_ a jtag chip ... | 09:30 |
| tnt | and the fpga only drives TDO actively in some states of the jtag FSM ans is HiZ at other times. | 09:31 |
| tnt | although during the whole shifting it should be active (and TMS=0 means it should stay in that state). | 09:31 |
| tnt | I only ever used glasgow with those boards and it has jtag pinout autodetect ... | 09:32 |
| pepijndevos[m] | well what makes me say that is the little blips you get when you hook up the SDO make it look like it's not an high impedence input | 09:32 |
| pepijndevos[m] | wait, I have a glsgow | 09:32 |
| key2 | have you connected the VCC to your cable ? | 09:33 |
| key2 | I've seen this kind of behavior when the FTDI's VCCIO pin is fed from the VCC of the target board | 09:34 |
| pepijndevos[m] | no only ground, I'm powering it externally now | 09:35 |
| pepijndevos[m] | or do I need to connect the 3.3v together? | 09:36 |
| pepijndevos[m] | ok how do i use glasgow to do jtag | 09:38 |
| key2 | I don't know your cable. but I know that if the vccio of the FTDI is not powered, it will not output on the other pins what you want | 10:44 |
| pepijndevos[m] | ive managed to use glasgow as tnt suggested | 10:44 |
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| pepijndevos[m] | hurraaay!! I'm now connected to etherbone with wishbone tool | 11:10 |
| pepijndevos[m] | is there a --kernel equivalent to wishbone-tool? | 11:12 |
| pepijndevos[m] | do I pass load-name and load-address? | 11:13 |
| pepijndevos[m] | no luck so far | 12:11 |
| pepijndevos[m] | so wishbone-tool doesn't have a --kernel option and load-name doesn't seem to do anything... and litex_term doesn't seem to have any way to connect to a remote bus | 12:18 |
| pepijndevos[m] | wat... so I can tell wishbone-tool to host a wishbone server, and then I can pass "crossover" to litex_term which... seems to make it really slow. And still not load the kernel :((( | 12:22 |
| _florent_ | pepijndevos[m]: what are you trying to do? If you want to load a binary over etherbone: | 12:25 |
| _florent_ | litex_server --udp | 12:25 |
| _florent_ | litex_term crossover --kernel=firmware.bin --safe | 12:25 |
| _florent_ | with a crossover uart | 12:25 |
| pepijndevos[m] | heyyyyy!!! that did the trick | 12:26 |
| pepijndevos[m] | lol this board doesn't seem to have a reset button configured. | 12:27 |
| _florent_ | probably this: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75x.py#L132 | 12:29 |
| _florent_ | but since you are using Etherbone, you could set with_rst to Trye | 12:29 |
| _florent_ | True | 12:29 |
| pepijndevos[m] | ah yea | 12:51 |
| pepijndevos[m] | another future problem is how to program the stuff to flash. I'm now using glasgow with the svd file that loads the bios into ram. I have no idea how I'd get the bios and eventually also the kernel into flash. | 12:57 |
| _florent_ | you can look at icebreaker/fomu targets for BIOS XiP from Flash | 13:07 |
| _florent_ | regarding Flash programmation, pretty sure OpenFPGALoader supports it (otherwise probably ecpprog: https://github.com/gregdavill/ecpprog) | 13:08 |
| pepijndevos[m] | yea problem is my usb JTAG thingy seems broken so I'm using glasgow and that seems to have its own whole thing | 13:22 |
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| pepijndevos[m] | <_florent_> "you can look at icebreaker/..." <- hmmm by the sounds of it maybe I'm asking the wrong question. All I want to do is... you know, run standalone. I suspect running from SDRAM is a lot faster and the ice40 only run from flash because limited BRAM. So actually maybe what I want is to load the kernel into SDRAM at startup? But it still has to be stored somewhere... | 14:59 |
| _florent_ | pepijndevos[m]: ok, for this, it you still want to use the BIOS and make it jump to your firmware in Flash, you can just add a ROM_BOOT_ADDRESS constant to your SoC pointing to the based address of the firmware in Flash. | 18:07 |
| pepijndevos[m] | Basically, I don't know what I want. What does a typical deployment scenario look like on a board with plenty of space? | 18:09 |
| pepijndevos[m] | <_florent_> "https://github.com/litex-hub/..." <- actually I'm not sure I completely understand where the divide happens here. There is only one PHY, one MAC, and the MAC gets memory mapped *and* is used by the hardware IP stack? | 18:12 |
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| _florent_ | pepijndevos[m]: For standalone operation you can have Bitstream in flash + BIOS + firmware (with ROM_BOOT_ADDRESS specified in the SoC definition) | 20:03 |
| _florent_ | pepijndevos[m]: This will load the bistream, execute the BIOS and jump to your firmware | 20:03 |
| _florent_ | pepijndevos[m]: for the Hybrid MAC, things are happening here: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/mac/__init__.py#L82-L167 | 20:04 |
| pepijndevos[m] | Ah I see | 20:06 |
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| tpw_rules | (hi) | 21:47 |
| absurdfatalism | Hello folks I wanted to ask about video/vga timings from this core | 21:48 |
| absurdfatalism | https://github.com/litex-hub/litevideo/blob/master/litevideo/output/core.py | 21:48 |
| absurdfatalism | IIUC, under += sync, as in inferring a FF | 21:50 |
| absurdfatalism | https://github.com/litex-hub/litevideo/blob/41f30143075ece3fff5c33a332ed067d1837cbb3/litevideo/output/core.py#L154 | 21:50 |
| absurdfatalism | There is this expression | 21:50 |
| absurdfatalism | If(hcounter == 0, hactive.eq(1)), | 21:50 |
| absurdfatalism | Which IIUC means active is HIGH a cycle delayed from hcounter==0 | 21:52 |
| absurdfatalism | I come here wanting to confirm that since in testing a 640x480 design | 21:52 |
| absurdfatalism | I see active=1 when x=1,2,..640 | 21:52 |
| absurdfatalism | As opposed to what I would have expected | 21:52 |
| absurdfatalism | active=1 for x=0...639 | 21:52 |
| absurdfatalism | A off by one cycle kind of thing? | 21:52 |
| absurdfatalism | (I was looking to detect start of from x==0 y==0 and active==1 but was never seeing it!) | 21:52 |
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