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| swetland | whee. I'm starting to (re-)understand the qemu innards | 09:08 |
|---|---|---|
| swetland | Working on building up a riscv machine for it that's compatible with vexriscv and the litex peripherals to allow the same code to run in qemu and on a ULX3s: https://github.com/swetland/qemu/commits/wip | 09:08 |
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| xenador77 | Took me way longer than it should have, but I finally got a simple "blinky" to execute without error on my attempt at an upduino_v3 platform file. Haven't managed to get that onto the actual board yet, but it's still progress | 18:20 |
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| swetland | the uart peripheral is kind of strange. the RXEMPTY register does not get set after you read the last character from TXRX, you have to clear the pending event bit | 22:43 |
| cr1901 | edge triggered int? | 23:00 |
| swetland | I believe so but the weird thing is the RXEMPTY register remains 0 even after the character is read | 23:07 |
| swetland | I expect the PENDING bit to stay until cleared but the status registers for peripherals usually reflect the current state | 23:07 |
| swetland | https://github.com/enjoy-digital/litex/issues/1289 | 23:07 |
| cr1901 | Right, pending is the interrupt bit, RXEMPTY is the status bit | 23:13 |
| cr1901 | hmm | 23:13 |
| cr1901 | (I don't have a good answer, sorry :P) | 23:13 |
| swetland | no worries! | 23:21 |
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