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| swetland | Is there a way to change the main ram base address for a single board? I'm not quite sure how/where to override mem_map["main_ram"] | 02:01 |
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| jevinskie[m] | What is the situation with Linux on LiteX and USB on the orangecrab? Do I only get a serial port? I’m wondering how I can get networking on the orangecrab Linux | 03:28 |
| swetland | daughterboard with an ethernet PHY? 10/100 shouldn't be too hard. Gbe might be hairy | 03:38 |
| cr1901_ | I would run a ppp connection over serial to a Pi or something w/ Ethernet personally | 05:39 |
| cr1901_ | but I'm a bit nuts | 05:39 |
| jevinskie[m] | <cr1901_> "I would run a ppp connection..." <- That sounds more like it for me, I’m trying to keep it over usb. I wonder if I can have two serial endpoints or present as two CDC devices one for ppp and one for kernel logging | 05:59 |
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| swetland | well if it's over usb you might as well do CDC Ethernet | 06:10 |
| swetland | it's pretty simple and you're then exchanging ethernet frames over usb | 06:11 |
| swetland | and should just look like another interface on the host you plug it into | 06:11 |
| swetland | likely far less painful and more plug'n'play than PPP | 06:12 |
| tnt | yeah, but iirc the default bitstream uses a pure CDC (like ... hw logic thing, risc-v sees it as a hw uart) | 06:17 |
| swetland | ah, I see | 06:19 |
| tnt | I wonder if you can use gadget cdc/serial as a console device on linux. | 06:21 |
| tnt | (not that there is any support for gadget driver for the OC but ...) | 06:22 |
| tnt | swetland: btw, I'm disappointed you didn't go for the full 16 CGA colors :D | 06:23 |
| swetland | I could not get the damn intensity bit wired up right | 06:24 |
| tnt | I think you'd pretty much have to make a LUT | 06:24 |
| swetland | I realized that not only are migens bit slices BACKWARDS from verilog, they're also *range exclusive* instead of *range inclusive* | 06:24 |
| tnt | Ah well yeah, they're python semantics. | 06:25 |
| tnt | I told you ... I hate it. | 06:25 |
| swetland | I am not a python fan and this experience is not changing that | 06:25 |
| swetland | In general the shape of migen/nmigen/amarath is nice but I really think a DSL instead of just re-using python with its quirks and goddamn syntatic whitespace would be a huge improvement | 06:26 |
| swetland | building a system inside python is like building build systems inside gnu make | 06:27 |
| swetland | you can make a nice build system but everyone looks and says "oh I know this, it's make!" and suddenly it all goes to hell ^^ | 06:27 |
| amstan | I agree, reusing python dsl is quite poor if you need expressions and flow control. It works a lot better if your stuff is declarative only. | 06:28 |
| amstan | On the other hand it wouldn't be too hard to create a dsl and convert it to the amaranth internal datastructures | 06:29 |
| swetland | the other thing that's frustrating is you can occasionally end up deep in some python backtrace with no clear idea what caused it | 06:33 |
| amstan | i think that's fixable, the exceptions can be rewritten | 06:33 |
| swetland | https://github.com/enjoy-digital/litex/issues/1285 | 06:33 |
| amstan | ouch, that's quite the mountful | 06:35 |
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| swetland | so here's something that is proving nonobvious -- I'd like to reconfigure vecriscv in litex for main ram at 0x8000_0000, so that it's easier to compile code to run on both it and qemu | 07:52 |
| swetland | (I realize I can change qemu sources as well, but since I'm customizing the "soc" anyway...) | 07:53 |
| tnt | see lattice_crosslink_nx_evn.py as example and look at line 62 | 07:56 |
| swetland | that almost gets me there. cores/vexriscv.py declares io region @80000000 size 80000000. editing that to @C0000000/40000000 at least has it building, but that's ugly | 08:03 |
| tnt | Oh yeah, you might have another propblen ... | 08:04 |
| tnt | the Vex scala code actually defines what is considered "IO" ( which influences cachine / mmu / ... ). | 08:05 |
| swetland | ahhhh I was afraid of that | 08:07 |
| swetland | on the plus side I've already figured out how to rebuild vexriscv from the scala | 08:08 |
| tnt | https://github.com/litex-hub/pythondata-cpu-vexriscv/blob/master/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala#L161 | 08:09 |
| swetland | ohoho I am LUCKY | 08:10 |
| swetland | I'm using the "linux" variant which defines io as 256MB @ B000_0000, E000_0000, and F000_0000 | 08:12 |
| swetland | well not that lucky | 08:14 |
| swetland | bios does start but serial download is blowing up | 08:14 |
| tnt | B0 is still conflict right | 08:14 |
| tnt | oh I guess depend how much ram you have. | 08:15 |
| tnt | why are you using the linux variant btw ? | 08:15 |
| swetland | only 32MB at 8000_0000, so plenty of room | 08:15 |
| swetland | I want a target with full U/S/M modes and a MMU | 08:16 |
| tnt | if you're trying to run linux, moving the ram is going to be a pain, the address is hardcoded at a bunch of places. | 08:16 |
| swetland | doing some "how to write an OS" workshops with some friends | 08:16 |
| swetland | definitely not planning on running linux. | 08:16 |
| swetland | but it is beginning to look like it'll be simpler to move the main ram region in Qemu (was just hoping to not have people have to build a modified qemu, but such is life) | 08:17 |
| swetland | I thought RISCV would be fun -- it's a "real" cpu, but not terribly complex, it runs fine in Qemu and on ECP5 platforms | 08:19 |
| _florent_ | regarding main_ram address/linux, the address in LiteX is probably only hardcoded in the CPUs, ex: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L116 | 09:02 |
| _florent_ | For rocket, we are using 0x8000000: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/rocket/core.py#L113 | 09:02 |
| _florent_ | But I'm not familiar enough with VexRiscv internals to say | 09:03 |
| davebee | Got gdb connected to my vexriscv yesterday, thanks to tnt. I can breakpoint, but not step. But it was enough to let me work out why FreeRTOS wasn't running. Now it does, so I have an OS running on my CPU. Next : implement semaphores and queues. | 09:55 |
| davebee | My C++ library code uses std::atomic<>. Not sure if the vexriscv supports atomics. Where should I ask? | 13:05 |
| tnt | it depends on which vex variant you're using | 13:11 |
| tnt | only the 'linux' variant in litex is configuted for LR/SC + AMO operations. | 13:13 |
| davebee | okay, thanks. I'm using standard+debug. I'll take a look. | 13:31 |
| davebee | Atomics are really handy, but the library I'm using was targetted at an STM327xx which does support them. There is probably a software fix. | 13:34 |
| davebee | stm32f7xx | 13:34 |
| tnt | OTOH does std::atomic actually use the RISC-V atomic operations ? | 13:37 |
| tnt | I mean, usually you can do atomics without hw support just disabling interrupt ... | 13:37 |
| zyp | I think if you don't have atomic instructions, the compiler generates a software implementation that calls stubs that you can provide to disable interrupts | 13:37 |
| zyp | tnt, yeah, if available it does | 13:37 |
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| xobs[m] | tnt: It does, yes. Platforms that don't have arlmkxa just don't have that package. | 13:38 |
| xobs[m] | * It does, yes. Platforms that don't have atomics just don't have that package. | 13:39 |
| xobs[m] | The software fix is to bodge it in a machine mode handler. | 13:40 |
| pepijndevos[m] | On a board without a nice usb interface, what's the best way to work with it? I have a jtag thingy to program the fpga, but then on the ulx3s I'd use litex_term --kernel to serial boot my code, so would I need a uart thingy to do that? | 13:41 |
| zyp | here's what gcc does with atomic instructions: https://godbolt.org/z/WMaEzdzqj and without: https://godbolt.org/z/E5sYf4eWY | 13:44 |
| tpb | Title: Compiler Explorer (at godbolt.org) | 13:44 |
| zyp | for atomic increment, it ends up calling a stub called __atomic_fetch_add_4 | 13:44 |
| pepijndevos[m] | wait... does this mean it can serial boot over ethernet?? https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75x.py | 13:45 |
| rowang077[m] | pepijndevos: You can boot over ethernet yes or over UART. I have never done it though | 13:45 |
| tnt | xobs[m]: yeah, I know you can use machine mode emulation, but as zyp pointed out, I expected GCC and stdc++ to have sw only solutions ot that. | 13:46 |
| tnt | pepijndevos[m]: in theory with crossover uart and a xxxBone bridge you should be able to yes. | 13:49 |
| pepijndevos[m] | Does etherbone completely take over the phy, or can the SoC still do ethernet? Kinda the whole point of the colorlight board for me is the ethernet. On the other hand, if I can use etherbone to twiddle registers in my SoC such that I don't have to deal with ethernet at all... 🤔 | 13:57 |
| tnt | IIUC they can both work at the same time. | 14:01 |
| _florent_ | pepijndevos[m]: you can do both at the same time, but we don't yet have a add_xy method for it, you have to do it manually in your target file | 14:03 |
| _florent_ | https://github.com/litex-hub/litex-boards/blob/575d6818915b16f69279f0628b4472a007dc5106/litex_boards/targets/siglent_sds1104xe.py#L94-L139 | 14:04 |
| _florent_ | you then have two MAC/IP addresses: One for the CPU + software stack, one for the hardware stack + etherbone | 14:05 |
| pepijndevos[m] | https://github.com/litex-hub/litex-boards/blob/9914478854b83ec5750c07df995b2390977280c2/litex_boards/targets/colorlight_5a_75x.py#L166-L169 ahh so if you just pass both of these CLASH! | 14:06 |
| _florent_ | yes, each of these will want to have direct connection to the PHY, which is not possible... | 14:27 |
| mithro | _florent_: Did you see https://wiki.f-si.org/index.php/FSiC2022 ? | 14:47 |
| tpb | Title: FSiC2022 - F-Si wiki (at wiki.f-si.org) | 14:47 |
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| davebee | thanks for the comments on atomics. | 15:28 |
| cr1901_ | tnt: What's the difference between machine mode emulation and "gcc providing a stub for you to implement atomics"? | 15:39 |
| cr1901_ | Re: "I expected GCC and stdc++ to have sw only solutions ot that." | 15:39 |
| davebee | I'm building with -march=rv32im ie no atomics. gcc creates calls to __atomic_fetch_add_4() and __atomic_fetch_sub_4(). I don't have these as Litex builds the newlib runtime and does nto include any C++ stuff. But I should be able to writes something. | 15:42 |
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| _florent_ | mithro: not yet, I'll look | 16:45 |
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| mithro | It's in Paris which seems like your neck of the woods | 18:42 |
| tnt | cr1901_: machine mode emulation is basically you compile cod efor RV32IMA but you'd don't actually have Atomics instruction in hardware. The CPU traps as illegal instructions and you provide a "bios" that emulates them and then returns from the trap. | 18:51 |
| tnt | cr1901_: That's actually what I did to run linux on ice40 because the hw atomics were too big to fit. | 18:52 |
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| swetland | for single core platforms atomics via disabling interrupts is not horrible. multicore you need spinlocks too which gets uglier | 19:41 |
| tnt | yeah sure, but the thing here was single core. | 19:56 |
| cr1901_ | I don't remember the name, but I seem to vaguely recall that ARMv5 on Linux emulates atomics in a different way | 20:56 |
| cr1901_ | ("pretend the critical section is atomic, and back up/fail if it turns out another thread tried taking control") | 20:56 |
| cr1901_ | Damn, gonna kick myself for not remembering the name of what I'm thinking of | 20:57 |
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| swetland | tnt: biggest problem with debugging my memory -> 8000_0000 changes... forgot to change the load address in litex term | 21:24 |
| swetland | https://pastebin.com/wYniWwqv | 21:41 |
| tpb | Title: ulx3s memory relocation - Pastebin.com (at pastebin.com) | 21:41 |
| swetland | What I've found is that I can move memory by adjusting soc/cores/cpu/vexriscv/core.py but all my various attempts to override things from radiona_ulx3s.py have failed | 21:42 |
| swetland | and the io region definitely needs to be adjusted (keeping the CSRs where they are but ensuring it doesn't overlap the higher memory window | 21:43 |
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