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| swetland | the video terminal puzzles me. The bios seems to write to the terminal as a side effect of writing UART_TX and it looks like there's a source/sink linkage there. But once my code starts running UART_TX writes only go to the uart. Am I missing something? Did the bios adjust some setting before transferring control? | 00:21 |
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| swetland | So the video_framebuffer has a depth parameter (default "rgb888", option "rgb565") which smells like it should maybe cut the fifo size in half... but changing to 565 just results in an exception and python backtrace somewhere in the bowels of verilog generation | 05:04 |
| swetland | reducing the fifo depth from 65536 to 16384 cuts the DP16KB usage from 32 to 8 and does not seem to impact operation (scanout works as before) | 05:44 |
| _florent_ | swetland: Hi, just for info the OrangeCrab is almost full with the configuration provided in Linux-on-LiteX-VexRiscv. Using the SD-Card in SPI mode can indeed free up some resources. | 05:52 |
| _florent_ | swetland: Regarding the VideoFramebuffer, you can indeed reduce the default fifo-depth | 05:53 |
| _florent_ | swetland: not sure if switching from rgb888/rgb565 will have a real impact on resource usage, it will just use a different data-with converter | 05:54 |
| _florent_ | swetland: you can eventually output this signal to an IO and monitor it: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L623 | 05:56 |
| _florent_ | swetland: if you see underflow, your FIFO is too small or resolution too high for its size | 05:56 |
| _florent_ | with VexRiscv, you can also use this to point to an externally generated CPU: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L357 | 05:59 |
| swetland | cool. I'll give that a look (fifo underflow) -- it certainly is not resulting in any visible artifacts in scanout at 1/4 the size | 05:59 |
| swetland | here's a possibly more complex question -- how involved would it be to instead of ingesting characters from the uart, just have the video terminal expose its character/attribute memory like a PC character display? | 06:00 |
| _florent_ | this would require remplacing https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L462-L553 with CSR registers allowing direct write to the terminal mem | 06:09 |
| _florent_ | this should not complicated and could be an optional mode | 06:10 |
| swetland | are you thinking like an address csr and data csr? I was hoping more for direct mapped like a local sram but that feels like poor fit for the csr address space | 06:11 |
| tnt | you can manually add a wishbone bus to it and wire it directly there as a memory zone. | 06:12 |
| swetland | I guess a single 32bit register that encoded { X, Y, CH, ATTR } would work | 06:12 |
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| swetland | the situation I'm thinking of is having multiple threads/processes writing to their own slice of the display without stepping on each other or needing locking | 06:13 |
| _florent_ | this could also be directly mapped as suggested by tnt yes | 06:15 |
| swetland | I think either solution would get the job done. guess I need to start learning migen (or nmigen)? | 06:16 |
| swetland | so CSRStorage() looks to be a CSR which then holds the written value in a register, is there an analogue that's more passthrough -- eg I could wire up to writing to the char/attr memory? | 06:22 |
| tnt | Yes CSR() | 06:22 |
| tnt | self._cmd = CSR(14) and then self._cmd.re is the 'write enable' and self._cmd.r is the data. | 06:23 |
| tnt | (And yeah ... why it's 'r' and 're' is ... confusing to me, but that's the way it is) | 06:23 |
| _florent_ | swetland: I could provide a skeleton for this if you want, but only this afternoon (in 5-6 hours) | 06:24 |
| _florent_ | tnt: I was discussing of the re/r situation recently with bunnie, it seems to be confusing for everyone (me included) and we'll change this | 06:25 |
| tnt | _florent_: isn't that going to be a maintenance nightmare ? | 06:26 |
| _florent_ | tnt: we'll just keep retro-compatibilty for it, but will introduce new signals with more meaningful names and encourage use of them | 06:26 |
| tnt | Ok. | 06:26 |
| _florent_ | with the retro-compatibility in place, it should be ok and will allow progressive switch | 06:27 |
| swetland | _florent_: I'm poking at the register thing now, we'll see how far I get. | 06:27 |
| swetland | I notice that the definition of CSR, etc have docs in the python sources -- is there a page where all the assembled docs are gathered? | 06:28 |
| swetland | I guess I'm hoping for a sort of "api refrence" or maybe "module reference" for the core building blocks | 06:28 |
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| * swetland tries to figure out how to slice a Signal() up into subparts | 06:39 | |
| tnt | x[0:2] ? | 06:40 |
| tnt | it uses the python slice thing. | 06:40 |
| tnt | with the same semantic and [0] is still the LSB. | 06:40 |
| tnt | ( TBH this is the thing I absolutely _hate_ about migen and amaranth, this drives me crazy ) | 06:41 |
| tnt | ( so x[0:2] in migen/amaranth is the same as x[1:0] in verilog ) | 06:41 |
| swetland | yeah I just read the "numbers go right to left but slices go left to right" | 06:41 |
| swetland | and my head already hurts | 06:42 |
| swetland | also my first error was spaces v tabs x.x | 06:42 |
| swetland | I am not a lover of python | 06:42 |
| swetland | I am even less a lover of using it as a DSL because instead of getting meaningful errors I stare at incomprehensible backtraces | 06:43 |
| tnt | Ahaha. Yeah, usually I love python _but_ I use tabs ... violating PEP8 but I don't care. But when working with code from other projects, I don't have a choice. | 06:43 |
| swetland | but such is life | 06:43 |
| swetland | I have no idea how to comment out or disable all the CSI state machine stuff | 06:43 |
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| tnt | remove it ? | 06:44 |
| swetland | well yeah that's what I'm doing for now, but figure at some point it'd be cool to make this thing a build option. I guess I'll burn that bridge if I get there | 06:47 |
| swetland | what's self.specials += ... about? | 06:48 |
| tnt | That's for stuff that gets special cased during build. Mostly FPGA architecture specific things. (i.e. it gets translated to primitives and such) | 06:49 |
| tnt | (I know only has much as do it when the examples show to do it ...) | 06:50 |
| tnt | And to make it a build option you can just use `if with_direct_access: xxxx_your_logic_xxxx else: xxx_the_previous_logic_xxx` | 06:51 |
| swetland | https://www.irccloud.com/pastebin/GonugSFm/ | 06:52 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 06:52 |
| tnt | yeah the [16:22] should be in the parenthesis | 06:53 |
| tnt | of is wrxy a CSR ? then you need wrxy.r | 06:54 |
| swetland | oh I see | 06:55 |
| tnt | Also, probably should be 23 ? | 06:56 |
| swetland | oh yeah, the :7 syntax threw me off | 06:57 |
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| swetland | hmmm. I added AutoCSR to VideoTerminal so it plugged in my csr... | 07:21 |
| swetland | self._wrxy = wrxy = CSR(size=32) | 07:21 |
| swetland | and yanked out the uart feed state machine and replaced it with | 07:21 |
| swetland | self.comb += term_wrport.we.eq(wrxy.re) | 07:21 |
| swetland | self.comb += term_wrport.dat_w[:font_width].eq(wrxy.r[0:7]) | 07:21 |
| swetland | self.comb += term_wrport.adr[:7].eq(wrxy.r[16:23]) | 07:21 |
| swetland | self.comb += term_wrport.adr[7:].eq(wrxy.r[24:31]) | 07:21 |
| tnt | mmm, should be 0:8 ? | 07:22 |
| swetland | maybe but don't think the high bit is the deal breaker | 07:23 |
| tnt | probably not. | 07:24 |
| tnt | And it doesn't work ? | 07:24 |
| swetland | if it were wired up right my expectation would be writing 0x30 to the register would drop a '0' in the upper left of the display x=0,y=0,ch='0' | 07:25 |
| tnt | sounds right | 07:26 |
| swetland | do I maybe have to capture the write before pushing it into the memory (eg, is wrxt.r life when wrxy.re strobes such that I can just wire it straight up to the memory like this)? | 07:27 |
| tnt | No, shouldn't be needed | 07:27 |
| tnt | Possibly only concern is ... which clock domain is the write port living in. | 07:28 |
| swetland | ohhhh | 07:28 |
| swetland | not sure how that's specified. | 07:29 |
| tnt | Where is the VideoTerminal created ? | 07:29 |
| swetland | a helper in the soc base thing | 07:29 |
| tnt | yeah, it's all in a 'hdmi' clock domain which isn't the 'sys' clock domain that the CSR lives in. | 07:31 |
| tnt | So you need to get the memory write port in the 'sys' domain | 07:31 |
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| tnt | TBH no clue how to do that ... the get_port has a 'clock_domain' arg, but it does default to 'sys' already but when instanciating VideoTerminal, 'sys' domain gets renamed to 'hdmi'. No ideo how to tell it not to do that for the write port :/ | 07:33 |
| swetland | ah the VideoFrameBuffer has the clock domain ("sys") passed in | 07:33 |
| swetland | before my changes the uart source thing used to write into this memory -- wouldn't that be in the sys clock domain too? | 07:35 |
| tnt | in the ulx3s file, clock_domain="hdmi" when alling the helper. | 07:36 |
| swetland | ah | 07:36 |
| tnt | No, if you look at the add_video_terminal, it does a CDC between the UART from the system and the signals given to VideoTerminal | 07:36 |
| tnt | _florent_: ping ^^ | 07:37 |
| tnt | How can we deal with that? Is there a way to get the 'sys' domain that _stays_ 'sys' ? | 07:38 |
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| swetland | I assume the block ram has clock-per-port so just writing in the sys domain reading in the hdmi domain certainly feels the most straightforward | 07:40 |
| tnt | yeah. | 07:40 |
| tnt | The problem is how to convince migen to do that :) | 07:40 |
| tnt | Because the whole "VideoTerminal" modules operates in 'sys' by default (which is the default domain when not specifying anything). But then with the "ClockDomainRenamer", the add_video_terminal helpers "moves" it all to another domain ("hdmi") in the case of ulx3s. | 07:41 |
| tnt | But in this case ... we want a small part of it to _stay_ in the 'sys' domain because that's where the CSR lives. | 07:42 |
| swetland | I wonder if the memory primitive has a way to directly specify the clock domain(s) | 07:42 |
| tnt | yes. get_port(clock_domain="sys") | 07:43 |
| tnt | but doesn't matter ... because this is _still_ going to get reassigned by the ClockDomainRenamer from add_video_terminal which is called after the port was requested and will take everything from the sys domain (even the memports) into the "hdmi" domain. | 07:43 |
| swetland | well that's no fun | 07:44 |
| tnt | The only way (very very hackish) I see to do it would be to request the memory port in a "csr" domain, then in the add_video_terminal helper, inside the ClockDomainRenamer, also ask to rename "csr" to "sys". | 07:44 |
| tnt | The clockdomain handling of migen/amaranth has ways to back you into a corner :/ It makes like 90% of the stuff easier, but then makes the other 10% a absolute nightmare (compared to just manually wiring 'clk' signals) | 07:46 |
| swetland | yeah, I kinda miss verilog for all its warts. | 07:46 |
| swetland | I'm a bit confused as to how get_port() knows which port to get | 07:47 |
| swetland | is it inferring it based on the variable you're assigning it to? | 07:47 |
| swetland | font_rdport = font_mem.get_port(has_re=True) | 07:47 |
| tnt | what do you mean which port to get ? | 07:50 |
| swetland | the memory has read and write ports, yes? | 07:51 |
| swetland | vt = ClockDomainsRenamer({"sys": clock_domain, "csr": "sys"})(vt) whee! | 07:51 |
| tnt | the ports you get are always read capable. And only write capable if 'write_capable' was set to true. | 07:51 |
| tnt | And if the "read side" of a write capable port isn't used, it'll be optimized out | 07:52 |
| swetland | ah | 07:52 |
| tnt | That works ? | 07:52 |
| swetland | synthesizing | 07:52 |
| swetland | we shall find out in a few | 07:53 |
| swetland | sadly it does not | 07:55 |
| tnt | :/ | 07:57 |
| tnt | Can you post the generated verilog somewhere ? | 07:58 |
| swetland | radiona_ulx3s.v ? | 07:59 |
| swetland | do you want any of the other outputs? | 07:59 |
| tnt | no, just th e.v | 08:02 |
| swetland | frotz.net/misc/radiona_ulx3s.v.gz | 08:02 |
| tnt | looking at term_mem it seems right | 08:04 |
| tnt | I guess maybe you should assign the upper 8 bits or maybe with the 'undefined' yosys is deciding that it can optimize it all out. | 08:05 |
| * swetland nods | 08:05 | |
| swetland | you win | 08:11 |
| swetland | and I have a writeable character ram | 08:12 |
| swetland | thanks for the help! | 08:14 |
| tnt | \o/ | 08:14 |
| _florent_ | great! (sorry I'm not really working this morning since have the kids around this morning) | 08:16 |
| swetland | no worries | 08:16 |
| tnt | _florent_: no worries. But if you have a cleaner solution for the clock domain issue above later on, I'd be curious to know | 08:17 |
| swetland | I think I'm going to extend the LEDS peripheral with _SET and _CLR registers | 08:18 |
| * swetland is working on a little intro-to-os-fundamentals workshop and wants to put together a friendly platform for learning things. being able to have different threads interact with hw without tripping over each other is nice for people to see what's going on | 08:19 | |
| _florent_ | tnt: I'll have a look later yes | 08:24 |
| tnt | Tx. | 08:28 |
| swetland | frotz.net/misc/colorful.jpg | 09:15 |
| swetland | wired the attribute byte to fg/bg RGB | 09:15 |
| tnt | Hey, nice. | 09:17 |
| swetland | calling it a night, but I think I'll add HSCROLL and VSCROLL controls to let you slide the character grid around and a way to write into the font "rom" | 09:25 |
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| davebee | Fibnally seeing some JTAG io | 11:04 |
| davebee | Finally seeing some JTAG traffic on my ECP5 / vexriscv with external JTAG io pins. litex_server seems to shift lots of tdi=1 into the state machine. In shift-dr tap state. No sure what I should expect to see but it does not manage to get a valid IDCODE from the system. | 11:06 |
| davebee | "Info : JTAG tap: auto7.tap tap/device found: 0x40100401 (mfg: 0x200 (<invalid>), part: 0x0100, ver: 0x4)" | 11:07 |
| davebee | Should litex-server provide a listener socket that gdb can connect to? I'm struggling a bit here. | 11:09 |
| tnt | Are you sure it's supposed to work that way at all ? | 11:30 |
| davebee | no, I'm not. | 11:31 |
| tnt | I'm not familiar with the ecp5 jtagg primitive. But on xilinx for instance you can't "insert" something in the chain, you can just have user IR (4 of them) and then shift data wiht the DR. But it will never add a device in the chain. | 11:32 |
| davebee | ok. I'm not using the JTAGG primitive - because it wouldn't do what you say it doesn't do. I've added an external 4-wire JTAG interface, with a minor mod to pass the connections to soc.add_jtagbone(). It has io, but it is not doing what I expected. And I'm not sure how to diagnose the problem. | 11:34 |
| tnt | ok, now I'm confused ... because jtagbone is supposed to work with the primitives I mentionned above AFAIK. | 11:36 |
| tnt | Like JTAGPHY instanciates XilinxJTAG / ECP5JTAG / AlteraJTAG | 11:38 |
| davebee | There is an optional parameter to JTAGPHY(), jtag=None, that bypasses the use of the primitive. I've set this to io lines tdi, tdo, tck, tms. And connected an FTDI JTAG interface to these pins. As I saw no effect from using the internal JTAGG primitive. But I think my problem is that I don't know what I am doing! What I want to do is to be able to connect gdb to the vexriscv. | 11:40 |
| tnt | well ... huh ... you can pass something as argument to jtag to use instead of the primitive. But that something needs to implement JTAG ... | 11:42 |
| tnt | (i.e. emulate one of the primitive and do what it does which among other things implement the scanning for id code and also decoding the states etc ...) | 11:43 |
| tnt | if you just wire tdi/tdo/tms/tck that's not going to do anything. It's missing the whole JTAG state machine. | 11:43 |
| davebee | There is a JTAGPHY and a JTAGUART created in soc.add_jtagbone(). So the JTAGG has the TAP state machine in? | 11:44 |
| tnt | yes | 11:44 |
| davebee | okay, I'll try that again. So if it doesn't add the device into the chain, how do I talk to it? | 11:45 |
| tnt | AFAICT the debug variant has a memeory zone 0xf00f0000 that talks to the Vex Debug unit. | 11:47 |
| tnt | And you can talk to it through either JTAGBone, or UARTBone, or any other bridge method of litex to read/write the soc address space. | 11:47 |
| tnt | you read https://github.com/timvideos/litex-buildenv/wiki/Debugging ? | 11:50 |
| davebee | I'll take another look, thanks. The csr.csv has the debug region : "memory_region,vexriscv_debug,0xf00f0000,256,io" so that looks good. | 11:52 |
| tnt | next step would be to get litex_server running using jtag transport. | 11:54 |
| tnt | and you can check that's working using litex_cli --ident and this should return the SoC identity through it. | 11:55 |
| tnt | Once you have that working you can try to attach gdb to it. | 11:55 |
| davebee | thanks. | 11:55 |
| davebee | The litex_server config assumes an ftdi interface, but the colorlight i9 has an STM32 on the extension board which implements a cmsisdap JTAG / USB interface. I'll see if I can get an openocd config that works with that. | 11:58 |
| tnt | note that you don't _have_ to use JTAGBone at all ... | 12:01 |
| tnt | if you have a uart you can use UARTBone. | 12:01 |
| tnt | (TBH that's what I do because a 2 MBaud uart is often faster just because of the overhead in jtagbone) | 12:01 |
| davebee | perhaps I should try that. Thanks. | 12:02 |
| tnt | Yeah, it's actually much easier. | 12:08 |
| davebee | uart connected, build running ... | 12:09 |
| tnt | I spent like 4 days gettings JTAG to work on the ZynqUSP, hoping that with a 30 MHz clock rate, it would blow a 2Mbaud uart out of the water ... and I was sorely disappointed. | 12:09 |
| davebee | Interesting. I've spent many hours trying to get JTAG working. | 12:13 |
| davebee | $ litex_cli --ident --port 1235 | 12:14 |
| davebee | LiteX SoC on Colorlight I9 2022-04-27 13:06:40 | 12:14 |
| tnt | ok, so now just need to get https://github.com/SpinalHDL/openocd_riscv connected to it. | 12:24 |
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| davebee | working on that. I already had a build. Thanks for all your help. | 13:05 |
| davebee | Had to change the default listener port for the openocd connection to litex_server. But can now gdb the target. | 14:10 |
| davebee | I can set breakpoints, but my bootloader reloads clean code over it when I reboot. :) Thanks tnt, I'm now in more familiar territory. | 14:11 |
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| mithro | davebee: Etherbone is much, much faster than either UARTBone or JTAGBone | 14:32 |
| mithro | davebee: If you have ethernet, use that :-) | 14:32 |
| davebee | Can I use it as the same time as debugging my ethernet driver ? | 14:33 |
| mithro | davebee: Does the colorlight i9 have two ethernet devices? | 14:33 |
| mithro | davebee: I know other ones do | 14:33 |
| davebee | Yes. I don't have them wired up though. I've got a Waveshare LAN8720 connected. Took me ages to get it working. The default Litex boot didn't enable auto negotiation, so I had to add MDIO. | 14:35 |
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| davebee | I bought some magnetics and RJ45 for the 2 * Gbit PHYs, btg haven't ever wired them up. | 14:41 |
| davebee | The eventual target won't have a PHY on board. | 14:42 |
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| davebee | n | 15:30 |
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| pepijndevos[m] | hello, I'm trying to run some Rust code on my ULX3S board. I'm basically revisiting http://pepijndevos.nl/2020/08/04/a-rust-hal-for-your-litex-fpga-soc.html but when I run litex_term nothing happens. | 15:36 |
| tpb | Title: A Rust HAL for your LiteX FPGA SoC - Wishful Coding (at pepijndevos.nl) | 15:36 |
| pepijndevos[m] | I kinda forgot how to debug this stuff | 15:37 |
| pepijndevos[m] | or maybe the way LiteX works just changed? | 15:37 |
| pepijndevos[m] | wat I just had to reboot? | 15:45 |
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| _florent_ | pepijndevos[m]: Hello, I don't things have changed that much since your Rust HAL experimentations no | 16:27 |
| pepijndevos[m] | haha I just forgot you have to press reset | 16:28 |
| pepijndevos[m] | and did not write this down | 16:28 |
| _florent_ | ah ok :) | 16:29 |
| pepijndevos[m] | Over the last couple of years more than one person mentioned having found my blogpost useful. Time for an update! | 16:30 |
| pepijndevos[m] | I'm planning to use it on one of these colorlight boards with ethernet | 16:31 |
| _florent_ | pepijndevos[m]: timing is good then, since ethernet on colorlight boards has just been improved a few days ago :) | 17:07 |
| _florent_ | pepijndevos[m]: to enable 32-bit datapath and improve timings | 17:07 |
| pepijndevos[m] | sweet | 17:08 |
| pepijndevos[m] | But you can still only use one PHY of the two right? | 17:08 |
| _florent_ | you mean with daisy chain or two separate PHYs? | 17:10 |
| _florent_ | on some colorlights (5A 75B V8 IIRC), the two PHYs are working | 17:11 |
| _florent_ | on the 5A 75 V7, only one PHY is working, but the issue could be in the reversing of the IOs, it would need to be re-verified I think | 17:11 |
| _florent_ | I don't see obvious reason why the second PHY is not working on V7 except this | 17:12 |
| _florent_ | BTW, it seems people from LinuxCNC are also using these boards with Yosys/NextPnr/LiteX to create CNC driver boards: | 17:14 |
| _florent_ | https://www.forum.linuxcnc.org/27-driver-boards/44422-colorcnc-colorlight-5a-75e-5a-75b-as-fpga-controller-board | 17:14 |
| tpb | Title: ColorCNC Colorlight 5A-75E/5A-75B as FPGA controller board - LinuxCNC (at www.forum.linuxcnc.org) | 17:14 |
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| pepijndevos[m] | ah I have 5A 75B V8 I think. Someone on twitter said they only support one, which seems to be confirmed by the target command line options. But yea maybe with a bit of hacking you can use both. | 17:31 |
| _florent_ | ah yes, current target file only support one, but using two should only be a matter of duplicating things (and also of available board resources) | 17:45 |
| pepijndevos[m] | a ok thanks :) | 18:02 |
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| swetland | can I install litex without it dumping all its python stuff in ~/.local ? | 21:19 |
| swetland | I'd like to keep it all contained together rather than filling my homedirectory with stuff | 21:20 |
| * swetland learns about venv | 21:31 | |
| swetland | yay. python successfully contained | 21:41 |
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| swetland | tidied up my VideoTextGrid hackery a bit... | 23:29 |
| swetland | https://github.com/enjoy-digital/litex/pull/1286 | 23:29 |
| swetland | https://github.com/litex-hub/litex-boards/pull/386 | 23:29 |
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