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| tcal | Is there already a generic delta-sigma DAC LiteX core? Maybe there's so many variations about how to do the buffering that everyone just rolls their own? I made a simple one with no buffering, just a CSR to hold the current value -- it's just a few lines of Migen. With this simple core, software is responsible for correct timing/synchronization of the samples. | 17:13 |
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| tnt | Mmmm, the way the DMA works in prog mode is actually pretty annoying :/ | 18:59 |
| _florent_ | tnt: The DMA is only covering the use cases I needed, but it should not be too complicated to change the high level behavior. | 20:59 |
| tnt | Yeah, working on it. I was hoping to use the HW as-is and only change the sw, but the loop status is not suitable for what I needed so I had to tweak it. | 21:01 |
| tnt | I got a single buffer write/read cycle working. Now further tweaking the kernel driver ... | 21:02 |
| tnt | I might end up just substituting the LitePCIeDMAScatterGather with a more custom one. It'll depend if all the CSR writes to refill the descriptors end up being a slow down or not. | 21:04 |
| tnt | (i.e. like instead of having to rewrite each descriptors individually, I'd add a single CSR and if you write 50 to it, it auto-resubmits 50 descriptors with a single CSR write) | 21:05 |
| _florent_ | I also probably did the initial code in 2014, so would probably do it differently now, but now that things are used, I avoid changing things too much, but different DMAs could eventually be implemented. | 21:32 |
| _florent_ | Antmicro also implemented https://github.com/enjoy-digital/litepcie/blob/master/litepcie/frontend/axi.py | 21:33 |
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