Friday, 2022-03-04

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_florent_tnt: The current gateware/software architecture and loop mode, the FPGA is indeed imposing the speed of the transfers (on a pre-allocated circular buffer) and software synchronize to it. (so have to handle underflow/overflow when not able to keep up). It should not be too complicated to operate differently, but this is what is currently used for the dma loopback test.07:17
_florent_tnt: I'm going to look at the DMA RX_DELAY issue you saw, I added it to be able to compensate for unknown initial delay in the loopback chain (when doing a loopback over the RFIC for example), but I've mostly been testing it on a specific configuration and will do more tests with others07:19
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tnt_florent_: yeah, I think just using the programmable mode and re-submit descriptors when the user space reads the current buffer would work. I didn't check the hardware side, but I assume if it has no descriptors, it just stops transfers until it has one.08:45
tntThe RX_DELAY could very well just be that the host PC is too slow and the dropped buffers prevent it from syncing. The host test machine is a relatively weak i3-10105 and gen3 4x full bandwidth is quite fast.08:47
_florent_tnt: When using loop mode, you first fill all the descriptors in the table and the core will just loop on it, but it's indeed perfectly possible to use the disable loop mode. In this case, the DMA will just execute the full table and stop after that. You'll also get an IRQ for each executed descriptor.09:16
_florent_tnt: Not sure indeed an i09:17
_florent_tnt: Not sure indeed an i3 will be able to keep up with the gen3 x4 full bandwidth09:17
_florent_tnt: disabling random data will speed up software: but still not sure it will be enough09:18
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tnt_florent_: yup I tried disabling random mode but it didn't seem to help.19:14
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