Sunday, 2022-03-06

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cr1901_florent_: If using a USB UART, is there a way to prevent the serialboot routine from blocking until the serial device is open on the OS side?17:22
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_florent_cr1901: You can probably do this:https://github.com/360nosc0pe/scope/blob/main/sds1104xe.py#L13217:40
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cr1901ahhh okay, cool17:42
cr1901interval parameter is for what?17:43
cr1901actually, what do the parameters mean?17:43
Prometheus6765Hello all, I am a complete beginner and I have been reading all I could to simulate an minimal SoC with Litex. Could Somebody help me?17:45
_florent_cr1901: the code is here, happy to answer questions if not clear enough:https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L281-L29818:19
_florent_Prometheus6765: Hi, feel free to ask specific questions if issues while running the simulation18:19
cr1901_florent_: I think I get it. autoflush sits between the PHY and the TX buffer.18:35
cr1901If timeout has passed, begin flushing the TX buffer one char at a time every interval clock cycles18:36
cr1901Is timer.done equal to 0 when timer.wait is equal to 0?18:37
cr1901https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L29518:37
cr1901I.e. if the source _is_ in fact ready, does timer.done immediately assert, or will it still wait for timeout before starting to send out the char18:40
Prometheus6765Thanks. Is there a good tutorial other than the Wiki? 19:01
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ilia__sPrometheus6765: I have https://github.com/sergachev/litex-template which has everything to simulate a firmware running within a SoC (so that's litex_sim and verilator under the hood) with `poetry run python src/main.py --sim --run`21:43
ilia__sbasically main.py, platform_sim.py, soc_base.py and firmware in src/ there are sufficient to create a simulation21:44

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