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| _florent_ | smb784: you will have to add the SPI Flash IOs similar to the generator (similar to https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/sqrl_acorn.py#L33-L41) | 09:28 |
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| promach[m] | For litedram, how do I actually make sure that the design passes STA check given DRAM's high minimum working frequency requirement ? | 13:13 |
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| promach[m] | and what is the clock value constraint set for Spartan-6 , Artix-7 platforms ? | 15:20 |
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| mikek_DE1SOC | I wish... :) | 16:04 |
| mikek_DE1SOC | No Risc-v IRC client YET!! | 16:04 |
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| cr1901 | I figured someone ported irssi already :o | 16:24 |
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| trabucayre | cr1901: irssi is in buildroot, buildroot build rootfs for Risc-V -> So I assume irssi may be build for Risc-V | 17:04 |
| trabucayre | :) | 17:04 |
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| smb784 | alright so I finally got the build script to generate a verilog file that includes the pcie core AND the gpio flash core, however i have noticed that in the constraints file all of the properties for the PCIE constraints have a location of X | 20:00 |
| smb784 | (example) set_property LOC X [get_ports {pcie_clk_n}] | 20:00 |
| smb784 | this causes issues during implementation, shows up as a bunch of critical warnings and causes the io clock placer during implementation to fail with the message: [Common 17-69] Command failed: 'X' is not a valid site or package pin name. ["~/XilinxWorkspace/SQRL_quickstart/litepcie_core.xdc":8] | 20:02 |
| smb784 | is this something I'm doing wrong in the gen script, or is something else going wrong here? the SPI pins all have correct locations | 20:02 |
| smb784 | also i'm getting critical warnings like [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks -of [get_nets icap_clk]]'. ["~/XilinxWorkspace/SQRL_quickstart/litepcie_core.xdc":4987] | 20:05 |
| smb784 | and [Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. ["~/XilinxWorkspace/SQRL_quickstart/litepcie_core.xdc":4987] | 20:05 |
| smb784 | and finally one last critical warning: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. ["~/litex/litepcie/litepcie/phy/xilinx_s7_gen2_x4/source/pcie-PCIE_X0Y0.xdc":103] | 20:05 |
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| smb784 | also tells me this odd warning: [Place 30-415] IO Placement failed due to overutilization. This design contains 1574 I/O ports while the target device: 7a200t package: fbg484, contains only 282 available user I/O. The target device has 285 usable I/O pins of which 3 are already occupied by user-locked I/Os. | 20:12 |
| smb784 | for some reason its setting a bunch of I/Os as package I/Os on the FPGA. Maybe these are intended for the RAM and not the FPGA? | 20:14 |
| smb784 | I have posted the gen script I am using to create the verilog files, it is identical to litepcie's gen.py with the exception of the SPI interface parts: https://pastebin.com/Ybn7FUFM | 20:24 |
| tpb | Title: litepcie_with_spi_and_gpio_UPDATE - Pastebin.com (at pastebin.com) | 20:24 |
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| somlo | litex with fpu-enabled ("full" variant) rocket using opensbi, on the nexys4ddr: https://pastebin.com/nu1dSE16 | 22:12 |
| tpb | Title: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ - - Pastebin.com (at pastebin.com) | 22:12 |
| somlo | uses the "generic" platform on upstream opensbi, with only one patch applied on top (to add suport for liteuart): https://github.com/litex-hub/opensbi/commit/70f4d95c4b6a3e0772b69177d764dad0dc5ca340 | 22:13 |
| somlo | planning on submitting that patch to the opensbi mailing list, see how that goes :) | 22:14 |
| smb784 | Now that I have successfully generated a verilog file that incorporates an SPI flash into the PCIe core using my modified gen script (found here: https://pastebin.com/Ybn7FUFM), it looks like its not setting up the constraints correctly during the creation of the xdc file | 22:50 |
| smb784 | most of the ports have LOC X as opposed to their correct pin value (example: set_property LOC X [get_ports {pcie_clk_n}]) | 22:51 |
| smb784 | why is it that this gen script isn't generating the correct pinouts for the IOs? Isn't that all specified in the ac701.yml file that I use to generate the verilog & constraint outputs? | 22:51 |
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