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| _florent_ | smb784: If you want to use the full LiteX flow, you can see how to integrate the LitePCIe + the SPI Flash core from the SQRL Acorn design | 07:23 |
|---|---|---|
| _florent_ | smb784: if you want to use the standalone core, you can either modify LitePCIe Generator to include it (use the code from the SQRL Acorn design) or integrate an Flash core externally (the generator provide a MMAP interface) | 07:24 |
| _florent_ | smb784: for the first solution, it only requires copy/pasting of the SQRL Acorn integration code + add the Flash IOs to the generator | 07:26 |
| _florent_ | andresmanelli: Hi, you can have a look at the Minerva CPU integration: The CPU is written in nMigen and generated/integrated during the build | 07:28 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/minerva/core.py#L96-L123 | 07:28 |
| _florent_ | There is also https://github.com/enjoy-digital/litex/wiki/Reuse-A-Verilog-VHDL-nMigen-Core#reusing-a-nmigen-core | 07:29 |
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| andresmanelli_ | _florent_: Oh I've seen the second link, but the first one actually handles the build itself so I think that's what I'm looking for. I'll take a look , thank you ! | 07:39 |
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| acathla | https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/boot.c#L263 If you start copying at 4 (because it's the address) and use the full payload_length, aren't you copying 4 random bytes? | 10:27 |
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| _florent_ | acathla: Thanks, I'm going to look at this | 12:41 |
| _florent_ | acathla: This is fixed with https://github.com/enjoy-digital/litex/commit/02c0ed2de7ea059bc37a506c1116c200070dd90e, thanks! | 13:05 |
| acathla | _florent_, cool, thanks. I think that's the only real thing that made the flash goes wrong, it was overwriting without erasing. | 13:10 |
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| smb784 | Hey everyone, I'm trying to integrate the spi flash loader into the litepcie gen.py so I can create a standalone verilog file that contains both the PCIe & the SPI flash modules | 22:15 |
| smb784 | I would like to do this so that I can add this to my own design for the SQRL Acorn | 22:16 |
| smb784 | I have copied over the code from the sqrl_acorn.py that incorporates the spi_flash & gpio to a copy of the gen.py generator for the litepcie core, however I'm getting an error when I run it with the ac701.yml: | 22:17 |
| smb784 | litex.build.generic_platform.ConstraintError: Resource not found: flash_cs_n:None | 22:17 |
| smb784 | does this mean I need to specify something extra in the ac701.yml? Or is there something else I am missing? | 22:18 |
| smb784 | Here's a pastebin link to my edited gen.py that incorporates the spi flash & gpio: https://pastebin.com/3RxdB9mF | 22:20 |
| tpb | Title: litepcie_with_spi_and_gpio - Pastebin.com (at pastebin.com) | 22:20 |
| smb784 | and the yml i'm using to generate this modified core is just the stock yml for the artix 7 found on the litex github: https://github.com/enjoy-digital/litepcie/blob/master/examples/ac701.yml | 22:21 |
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