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| smb784 | Hey everyone, quick question about block diagrams and litex cores. I would like to integrate the litepcie core into my design so that I can upload my design via pcie. Is there a way to generate a block diagram of my design that I can then import to vivado and integrate with my verilog design? if not, is there a way to output a verilog version of the litepcie design so that I can accomplish the same task without the block design | 16:46 |
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| acathla | _florent_, I tried to use litex_term as it is, but serialboot's writes are not aligned so I had to modify it, and boot.c and other files. Now it can serialflash (if code is not executed from flash of course) but it breaks compatibility with actual litex_term. | 18:18 |
| acathla | I'm not sure if it's usefull to anyone | 18:18 |
| acathla | And litex_termm send the size of payload as a byte, so either you add 1 somewhere to the size and you won't be able to send frames with payload = 0, or you won't be able to send payloads of 256 bytes. | 18:21 |
| acathla | So, may be it's time to break litex_term a bit and fix all those bugs (we could probably keep compatibility with different magic numbers to detect different versions). | 18:23 |
| _florent_ | acathla: This features has been contributed in the past, but I removed it since was not easy to maintain and not really used. For flashing, I have a preference to have use external tools (OpenFPGALoader, OpenOCD) or a proper DFU bootloader (ex Foboot) and I'm not sure this should be part of the BIOS. | 18:36 |
| smb784 | florent, is there a way to generate a block design or output a verilog version of litepcie so that I can give my custom verilog design the ability to be uploaded via PCIe? | 19:15 |
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| acathla | _florent_, ok, i'll keep a patch for my own use then | 19:59 |
| _florent_ | smb784: you can use the litepcie generator script: https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py | 20:11 |
| _florent_ | ex with this config file: https://github.com/enjoy-digital/litepcie/blob/master/examples/ac701.yml | 20:12 |
| _florent_ | litepcie_gen ac701.yml will generate a standalone core | 20:12 |
| _florent_ | you can also re-integrate the flash core if you want to be able to update the design over PCIe | 20:15 |
| _florent_ | https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sqrl_acorn.py#L114-L124 | 20:15 |
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| smb784 | ok, thanks florent. If I wanted to reintegrate the flash core, do use a flag with litepcie's gen.py? | 20:38 |
| smb784 | or, more specifically, how do I reintegrate the flash core with the pcie core and then output it to a verilog file? | 20:42 |
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| andresmanelli | Hello, I think more than one asked this already but.. is there any concrete exemple of adding a nMigen core to a target built by LiteX? | 22:17 |
| andresmanelli | I know (didn't do it for the moment) that generating the verilog source and adding this as an Instance should work, but I'm not sure how this is included in the build process | 22:19 |
| andresmanelli | Thanks! | 22:20 |
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