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| mra | hey! just had a bit of a question about best practices involving the ghdl plugin. if i need to be able to instantiate chip-specific primitives that yosys won't infer (plls, for instance), would the "correct" way to do that be to fully elaborate my project with ghdl, then use write_verilog to save everything to a verilog file and then use that for | 16:54 |
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| mra | synthesis? it seems a bit messy, but i can't figure out any other way to refer to primitives in vdhl... | 16:54 |
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| lofty[m] | ghdl has already elaborated the design to yosys; you can use it directly | 16:55 |
| mra | what the hell... could have sworn that i tried that. well, productive waste of a few hours i guess | 16:57 |
| mra | thanks! | 16:57 |
| lofty[m] | I guess it wouldn't work if the GHDL elaboration doesn't match the yosys cell definition, though | 16:58 |
| mra | yeah, but that should be fine as long as i'm careful to correctly match things up. i could also write vhdl wrappers for the primitives that i need for a bit more flexibility, i suppose | 16:59 |
| lofty[m] | what's the chip you're targeting? | 16:59 |
| mra | the ice40. got an icebreaker fpga board recently | 17:09 |
| lofty[m] | that shouldn't be too painful then. | 17:09 |
| mra | unfortunately a new enough version that they don't seem to have posted the pinout or schematics, so there's a bit of trial and error... | 17:10 |
| mra | but other than that it's not so bad | 17:10 |
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| mra | the only other struggle i've had build-wise is that if i split entities into their own files, which seems like the norm, ghdl seems to require that the files be analysed in dependency order, which makes automating the build a bit annoying, unless i modify my makefile every time i add a new entity | 17:13 |
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