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| orhosko | Hello everyone, I was using nextpnr-himbaechel and I kinda stuck. Is this the right place to ask for? | 11:59 |
|---|---|---|
| orhosko | My problem was using ROM16 modules is possible in gowin ide but I couldn't managed to use with nextpnr. I haven't found any issues about it. Is it not implemented or am I missing something? | 11:59 |
| Semisol[m] | orhosko: ROM16 is a LUT with all inputs as address select | 12:01 |
| Semisol[m] | It will synthesize like regular LUTs, and I believe Yosys can infer it if you use an asynchronous read-only memory | 12:01 |
| lofty | yeah, the answer is to just use soft logic for it | 12:02 |
| orhosko | firstly thanks a lot for quick response. I was getting 'ERROR: Unable to place cell 'rom.rom16_inst_5', no BELs remaining to implement cell type 'ROM16'' and there are many LUTs available(using only 1%). If I understand correctly its due to my implementation. I was trying the IP generator from the gowin ide so maybe I need to look into produced | 12:04 |
| orhosko | module.. | 12:04 |
| Semisol[m] | orhosko: `ROM16` is an abstraction | 12:07 |
| Semisol[m] | if possible, you should use a platform-independent async ROM | 12:08 |
| Semisol[m] | that, and things like case statements, will automatically get turned into ROMs, and could get further optimized by yosys | 12:08 |
| Semisol[m] | if you must manually do it, use a platform LUT, set the init values to the ROM contents, and use I0-I3 as address select | 12:09 |
| orhosko | Ohh thanks it makes sense now. The produced IP from the IDE looks something like this | 12:20 |
| orhosko | ``` | 12:20 |
| orhosko | ROM16 rom16_inst_0 ( | 12:20 |
| orhosko | .DO(dout[0]), | 12:20 |
| orhosko | .AD(ad[3:0]) | 12:20 |
| orhosko | ); | 12:20 |
| orhosko | defparam rom16_inst_0.INIT_0 = 16'h0002; | 12:20 |
| orhosko | ``` | 12:20 |
| orhosko | and if I understand correctly I can implement this by myself easily. It is just LUTs. However there are still some points I haven't understood. First one is why i can use similarly complex generated pROM directly but not ROM16. If someone creates that abstraction, can/should it be implemented. Here is the pROM implementation its similarly complex: | 12:20 |
| orhosko | ``` | 12:20 |
| orhosko | pROM prom_inst_0 ( | 12:20 |
| orhosko | .DO({prom_inst_0_dout_w[23:0],dout[7:0]}), | 12:20 |
| orhosko | .CLK(clk), | 12:20 |
| orhosko | .OCE(oce), | 12:20 |
| orhosko | .CE(ce), | 12:20 |
| orhosko | .RESET(reset), | 12:20 |
| orhosko | .AD({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,ad[3:0],gw_gnd,gw_gnd,gw_gnd}) | 12:20 |
| orhosko | ); | 12:20 |
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| lofty[m] | from some quick browsing through the nextpnr source and the gowin primitive guide: pROM maps to BSRAM (block RAM), but ROM16 maps to SSRAM (LUT RAM). | 12:37 |
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| orhosko | I also looked for nextpnr source code and couldn't find anything about ROM16. Thats why I thought it's not implemented. Did you find anything in source code or is it from the primitive guide? | 12:50 |
| lofty[m] | from the primitive guide: https://cdn.gowinsemi.com.cn/UG285E.pdf | 12:54 |
| orhosko | Thanks a lot to both of you. I will try to implement myself now. I still not sure whether ROM16 should be part of the nextpnr since IDE provides it directly. Maybe I will open a issue/pr later. thx again | 13:10 |
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| gatecat | the easiest option to implement it would probably just be a yosys techmap rule that converts it to a LUT, given that's all that's happening in any case | 14:56 |
| gatecat | it's the kind of thing techmap rules are very nice for | 14:57 |
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