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| lethalbit | ya know, like, nya~ | 07:27 |
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| xutaxkamay | hi, quick question, is there a way for yosys to ignore warnings about logic loops? i'm using a feedback loop for an asynchronous design, for now i'm just ignoring the check pass, but i'm not sure that's very wise | 15:56 |
| xutaxkamay | the reason of why i want to ignore the check and share pass is that it takes more probably than a week for it to finish | 16:00 |
| xutaxkamay | the synthesis works fine when there's a clock detected though | 16:01 |
| lofty | xutaxkamay: logic loops are undefined behaviour inside the Yosys IR - RTLIL | 16:04 |
| lofty | can you rewrite your feedback loop as a latch? | 16:04 |
| jix_ | you can also manually break the loops by inserting a black box "buffer" module, then run synthesis, and finally map those loop breaking black boxes to a direct connection | 16:07 |
| xutaxkamay | lofty: i'm a bit a newbie in the hdl world, but the feedback loop is essentially here to maintain on purpose an infinite loop on a FSM where i can handle some handshake system with i/o ports to manage memory | 18:32 |
| lofty | that sounds like you could use a latch. | 18:32 |
| xutaxkamay | lofty: do you mind explaining what you have in mind? i know what a latch is but i'm not really seeing what you want me to do with it exactly | 18:39 |
| lofty | well, you're using it to maintain an FSM state, right? that's memory | 18:40 |
| lofty | a latch is a unit of memory, so trigger the latch as necessary | 18:40 |
| xutaxkamay | (i'm using vhdl) i use a signal to maintain the FSM state and use it inside the process sensitive list, which exactly causes the feedback loop yeah, so you mean just to add an enable input ? | 18:44 |
| lofty | unfortunately I'm not familiar with VHDL, but yosys provides a cell called `$dlatch` which is a literal latch | 18:45 |
| xutaxkamay | do you mind showing me a simple example in verilog that would translate to that dlatch? sorry for wasting your time | 18:46 |
| lofty | you can just use it like a module | 18:46 |
| lofty | but, uh | 18:47 |
| lofty | xutaxkamay: `yosys -p 'help $dlatch+'` | 18:49 |
| lofty | that is literally what the $dlatch cell is | 18:50 |
| xutaxkamay | yeah it has en enable input i see | 18:50 |
| xutaxkamay | but | 18:50 |
| xutaxkamay | i don't know how to say it but then isn't that basically requiring a clock? | 18:50 |
| lofty | no, because it's a latch and not a flop | 18:51 |
| xutaxkamay | okay but then enable needs to be oscillating between 0 and 1 in that case to keep triggering the latch | 18:53 |
| xutaxkamay | or im wrong ? | 18:53 |
| lofty | you will have some condition to hold state, right? in this case, the handshake with memory | 18:53 |
| lofty | (I will point out that writing asynchronous logic with the open tooling is a very bad idea, but I can't stop you) | 18:55 |
| xutaxkamay | lofty: so yeah you want me to use the input ports inside sensitive list and use them like i would do for a latch, but the problem is that i also need the inputs to know the state of another component (especially when a boolean input is false), i admit it it was probably a bad idea to start with, but i wanted to try it anyway | 18:59 |
| xutaxkamay | i've been looking to other languages like LARD but they don't provide sources anymore or even binaries | 19:01 |
| xutaxkamay | but yeah for sure, making it with a clock will prob make my life much easier | 19:07 |
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