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| lofty | philtor: anyway, if you open the docs, you can find a description of the architecture, and in particular the "LUT trees", which are certainly one of the FPGA architectures of all time | 00:01 |
|---|---|---|
| philtor | Looks like their dev boards are $250 from digikey | 00:01 |
| philtor | I think I'd probably lean towards ECP5 board (ULX3S) which is about 1/2 that price. | 00:02 |
| lofty | I mean, sure, but you wanted "new" stuff, and I think it's a little difficult to qualify the ECP5 as new | 00:03 |
| philtor | Yeah | 00:03 |
| lofty | It sounds a little stupid to say, and god knows I've had my frustrations with them | 00:04 |
| lofty | But there's a wave of "indie FPGA" for whatever one might define as not {Altera, Xilinx, Lattice}, and I think it's healthy to encourage diversity in this stuff | 00:05 |
| philtor | I guess Nexus is Lattice's 'new' FPGA | 00:05 |
| lofty | Yeah, it's the family intended to replace both ECP5 and iCE40 | 00:06 |
| philtor | It's supported by Yosys? | 00:06 |
| philtor | (or has yosys support) | 00:06 |
| lofty | And nextpnr. | 00:06 |
| lofty | I think the main challenge is that it's off to a...pretty slow start | 00:07 |
| philtor | any dev boards? | 00:07 |
| lofty | A few from Lattice. Too new to see much interest or uptake from the open community because the ECP5 is generally good enough. | 00:09 |
| lofty | (lattice have something of a problem of their old product lines eating their new) | 00:09 |
| philtor | Yeah, looking at their site there seems to be a lot of confusing fragmentation | 00:10 |
| lofty | The nexus family is basically the same underlying fabric with different sizes and features | 00:11 |
| philtor | searches for nexus fpga development boards point to CertusPro-NX | 00:11 |
| philtor | Seems to be a lot of stuff on those parts like SERDES, etc, that I'm not interested in much. I'd just like a lot of fabric. | 00:12 |
| lofty | How "a lot" is "a lot"? :p | 00:12 |
| philtor | and those boards are $450 which is even worse than the GateMate board | 00:12 |
| lofty | They're also probably bigger than the gatemate chip, although that's a really blurry comparison | 00:13 |
| philtor | "a lot of": well, maybe the larger ICE40s would suffice. | 00:13 |
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| lofty | Protip: there is no 12k ECP5 die | 00:14 |
| lofty | It may say 12K on the part number, but it's actually 25K. | 00:14 |
| lofty | But you didn't hear that from me. | 00:14 |
| philtor | Looking at doing some bitnet testing (the 2bit weight transformer) with an... unorthodox RISC-V implementation. | 00:16 |
| philtor | which is why I don't care much about peripherals like SERDES, MIPI, etc. on the FPGA | 00:17 |
| lofty | I've been in the open hardware community enough that orthodox RISC-V implementations feel like the exception | 00:20 |
| lofty | (microcoded RISC-V, anybody?) | 00:21 |
| lofty | (and I have my own sketch of a dumb RV core) | 00:21 |
| philtor | yeah... well this one is pretty out there. Not my idea, but kind of interesting. Can't say a lot about it. Dynamically modifiable microcode is part of it. | 00:24 |
| philtor | But there's more than the RISC-V piece hence the need for gates... or LUTs. | 00:26 |
| philtor | Oh, hmmm... maybe the GateMate would actually be good for this "Each CPE is configurable as a 2-bit full-adder or 2×2-bit multipliers " that's kind of right up our alley. | 00:36 |
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| lofty | philtor: you're trading off potential performance for flexibility, but then there are limits to performance anyway. | 01:45 |
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| philtor | lofty: is yosys able to take advantage of these GateMate features? (configuring CPEs as 2bit full adders or 2x2 multipliers) | 18:53 |
| lofty | Yes, it can even make use of the mux4 capability | 18:54 |
| tnt | Isn't yosys their official tooling ? If so I'd hope it can use all their features :) | 18:55 |
| lofty | It's their official *synthesiser* | 18:56 |
| tnt | well yeah, yosys never does pnr or did you mean something else ? | 18:57 |
| lofty | I've seen enough people use "supported by Yosys" to mean "supported by Yosys and nextpnr" that I prefer to make the distinction clear | 18:58 |
| tnt | Ok fair enough. I know the distinction :D | 18:59 |
| lofty | Like, you need their proprietary place and route tool; yes, you could say it's supported by Yosys, but that's not always what people are actually asking for | 19:00 |
| tnt | I know. I wish their pnr tool was oss too ... or better just nextpnr alas ... it's neither. | 19:03 |
| tnt | At least it's no longer a win32 binary they tell you to run on wine ... | 19:04 |
| tnt | so I guess it's "progress" | 19:04 |
| lofty | [20:03:43] tnt: I know. I wish their pnr tool was oss too ... or better just nextpnr <--- ;) | 19:08 |
| lofty | (though from what I've heard, even if they opened their tooling, it would probably not be so great) | 19:08 |
| tnt | :) | 19:09 |
| philtor | Hmm... their doc has a diagram that points to the pnr part of the flow and says "nextpnr arch planned in 2023" | 20:39 |
| lofty | unfortunately we at yosyshq have our hands full with a different nextpnr arch presently, so, uh | 20:41 |
| philtor | so what you're saying is that while yosys (the synthesis part) may work well with GateMate, the P&R story isn't great. | 20:42 |
| lofty | I personally have no experience with GateMate's P&R, so I can't say anything either way | 20:43 |
| philtor | Some aspects of the arch look really suitable for what I'm trying to do (help someone with an idea get a working POC so he can persue funding), but other aspects give me pause. | 20:44 |
| lofty | like that P&R tooling, I assume | 20:45 |
| philtor | yeah, sounds like it's kind of a questionmark at this point, like is it even really a working flow? | 20:45 |
| lofty | I believe so | 20:45 |
| lofty | (I also think part of the P&R story is they based it off somebody else's code and they do not have permission to release it) | 20:46 |
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