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| Myrl-saki | I think I can make my shifter even go more zoom. | 03:56 |
|---|---|---|
| Myrl-saki | Hm wait nah | 03:57 |
| Myrl-saki | I mean, it's slightly easier on the router? | 03:57 |
| Myrl-saki | I need to learn how PIPs work! | 03:57 |
| Myrl-saki | Oh wait, I can't yet. | 03:58 |
| Myrl-saki | Well, that kinda sucks. My idea was to make the first stage use `x + (b ? x : 0` | 03:58 |
| Myrl-saki | Oh, I know how to solve some other things phew. | 04:02 |
| Myrl-saki | The only problem is that I'm implementing right shifts then. | 04:02 |
| Myrl-saki | So I need to rewrite it to use left shifts. | 04:02 |
| Myrl-saki | Question is, is this better than `b ? {x[N:1], ...} : x`? | 04:02 |
| Myrl-saki | Ah, the answer is no for GOWIN specifically I think, because there's only 6 ALUs per CFU, while there are 8 LUTs per CFU. :( | 04:05 |
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| lofty | [04:57:16] Myrl-saki: I need to learn how PIPs work! <--- there's not much to learn; a Programmable Interconnect Point connects one wire to another | 06:28 |
| Myrl-saki | Oh yeah, I get that part. What I'm curious about is for example, how signals get from (R,C) to (R',C') | 06:29 |
| Myrl-saki | And also how things get connected uh, from external signals? to the slices? | 06:31 |
| Myrl-saki | I guess what I'm saying is I'm curious about the topology here. If for example, I want to create a D latch, I think it's possible for a LUT to feedback to itself, and put an enable pin. How does it do that? | 06:33 |
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| lofty | Myrl-saki: the LUT will have an output signal in the SLICE; PIPs will connect it to some wires, which are arranged in a grid shape - I think you're using Gowin, so it would be the X1 wires. | 06:35 |
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| lofty | At the end of each wire is a switch box made up of PIPs to connect more wires together, which is how it makes the turns needed to end up back at the inputs of the slice | 06:36 |
| lofty | And then a connection box made up of PIPs is used to pull wire signals into slice inputs | 06:36 |
| Myrl-saki | Ahhh thanks. And I'm guessing the router's job is to figure out which PIPs to enable? | 06:39 |
| Myrl-saki | Huh yeah, I think I see. | 06:47 |
| Myrl-saki | Oh wait, am I slightly wrong on that? | 07:08 |
| lofty | Myrl-saki: yeah, basically. | 07:08 |
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| Myrl-saki | I think I see it now by the way! :) Specifically the "turns needed to end up back" part. | 07:10 |
| Myrl-saki | https://github.com/YosysHQ/apicula/blob/066a70b6d41a0c2d8adf13ae33d4664d4a422230/apycula/gowin_pack.py#L1013-L1030 | 07:10 |
| Myrl-saki | This seems like it enables PIPs to route one wire to another within a tile. | 07:12 |
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| Myrl-saki | Hm, how do higher-width MUXes get generated? $pmux? | 09:16 |
| Myrl-saki | I guess pmuxtree also to some extent. | 09:16 |
| Myrl-saki | Oh, muxcover? | 09:18 |
| Myrl-saki | Ah found it. | 09:20 |
| Myrl-saki | Hmmm | 09:28 |
| Myrl-saki | I'll probably need help from someone to understand the timings. | 10:03 |
| Myrl-saki | Oh cool, turns out there are mux tests! | 10:35 |
| Myrl-saki | Hehe. :) | 10:38 |
| Myrl-saki | I'll push this in a bit I think. | 10:38 |
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| lofty | povik: what did you change in toymap? it's not too obvious from the commit history. | 10:47 |
| Myrl-saki | Info: Max frequency for clock 'sysclk': 29.71 MHz (PASS at 24.00 MHz) | 10:57 |
| Myrl-saki | oh no what have I done | 10:57 |
| Myrl-saki | Hm, what does shiftx do | 11:00 |
| Myrl-saki | Or rather, how does shiftx get transformed as passes run? | 11:02 |
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| keesj | Hi, I am wondering about the compressed instruction set option of PicoRV32. Does COMPRESSED_ISA =1 imply a choice between the normal and compressed set or should is be seen as addition? | 12:12 |
| keesj | https://github.com/YosysHQ/picorv32 | 12:12 |
| tnt | It's an addition. | 12:17 |
| lofty | keesj: the compressed instruction set is not standalone, so it has to be an addition anyway | 12:21 |
| Myrl-saki | Okay cool, I have something which I think can be reviewed. | 12:22 |
| lofty | sure, I'll take a look if you link it | 12:22 |
| Myrl-saki | Yay. :) | 12:22 |
| Myrl-saki | Hm wait. | 12:25 |
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| Myrl-saki | Okay, so it does seem to actually have some effect, phew. | 12:35 |
| Myrl-saki | lofty: https://github.com/YosysHQ/yosys/pull/4004 | 12:35 |
| Myrl-saki | Draft for 2 reasons: (a) I'm not sure if the timings are right (b) I have no idea how to integrate it with synth_gowin. | 12:36 |
| Myrl-saki | I took the timings based on LUT5 and LUT6. | 12:38 |
| keesj | tnt: thanks (that is what GPT was also saying but I wanted to double check) | 13:00 |
| lofty | keesj: are you actually trusting GPT on...*anything?* | 13:01 |
| keesj | Pretty much yes, trust but verify | 13:03 |
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| Myrl-saki | Seems like there's actually a pass to convert LUTs back to MUXes. I'm not sure when it actually triggers though. | 13:23 |
| Myrl-saki | Okay, so I think the reason why I need to set a proper cost is because Yosys might decide to promote a 3-input mux into a 4-input mux? | 13:39 |
| Myrl-saki | Hm | 13:40 |
| lofty | Myrl-saki: there's basically no reason to use lut2mux though | 14:02 |
| Myrl-saki | I checked and even before this patch, synth_gowin seems to know how to convert a MUX4 to a 2xLUT3 + MUX2 sometimes. | 14:03 |
| Myrl-saki | And I'm not sure how it does it lol | 14:04 |
| Myrl-saki | Oh wait. | 14:05 |
| Myrl-saki | Ah. | 14:05 |
| Myrl-saki | I think this was a misinterpretation on my part. | 14:05 |
| Myrl-saki | I think what muxtree is comparing is then whether to use a LUT5 or a MUX4. | 14:06 |
| Myrl-saki | Errr muxcover | 14:07 |
| Myrl-saki | Yeah, okay, cool. | 14:08 |
| Myrl-saki | In hindsight though, yeah, turns out I could have just implemented this with a LUT5 lol | 14:08 |
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| povik | lofty: lutrewrite generalizations are the improvement | 16:12 |
| povik | it considers more structures to rewrite the network into (different LUT sizes and also what some of the literature calls a 'shared' variable) | 16:12 |
| povik | also rewriting got enabled for LUT6 mapping | 16:13 |
| povik | Myrl-saki: so, about that PR, very curious | 16:15 |
| povik | does that demonstrably improve QoR? | 16:15 |
| povik | wouldn't the MUX gates like that, being only an optimized composition of other technology gates, but being registered for a mapping target of its own anyway, be called a 'supergate' in the literature? | 16:18 |
| lofty | Well, ABC9 can't directly map to this anyway, so | 16:18 |
| povik | ah | 16:18 |
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| lofty | ...you would have to create a gate library or something and map it as if it was an ASIC | 16:18 |
| lofty | which is...incredibly inefficient :p | 16:19 |
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| povik | ah of course, gowin as an FPGA flow will instruct ABC9 to map to the registered LUT variaties only, other then that won't be inferred | 16:21 |
| povik | i got distracted by the `(* abc9_box *)` annotation, but that was... err, only yesterday when we covered that that means something else | 16:22 |
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| lofty | ;) | 16:22 |
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