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| FL4SHK | okay so this bug appears to be in sv2v | 14:02 |
|---|---|---|
| tnt | is it ? What's wrong with the verilog ? It looked fine to me. | 14:03 |
| FL4SHK | the problem is the order in which task arguments are called | 14:03 |
| FL4SHK | I had used named (.name(...)) arguments in the SV | 14:03 |
| FL4SHK | and the order wasn't right in the final Verilog | 14:04 |
| tnt | Oooohhhhh yeah, I completely missed that when reading the verilog. | 14:04 |
| FL4SHK | I just found it | 14:04 |
| FL4SHK | this explains everything | 14:04 |
| FL4SHK | hm | 14:06 |
| FL4SHK | it appears that there is still an issue with yosys | 14:06 |
| FL4SHK | because even with not using named arguments | 14:06 |
| FL4SHK | it still assigns 'x | 14:06 |
| FL4SHK | without rst there's no issue | 14:07 |
| FL4SHK | but with rst there is | 14:07 |
| FL4SHK | or hm? | 14:09 |
| FL4SHK | maybe with rst there's still a bug | 14:10 |
| FL4SHK | I could have sworn I had put these in the right order | 14:10 |
| FL4SHK | tnt: so yeah it still doesn't work | 14:18 |
| tnt | :( | 15:00 |
| FL4SHK | tnt: it might only be a problem with Verilog output | 16:43 |
| FL4SHK | Is there a different way to output a netlist besides write_verilog? | 16:44 |
| jix_ | didn't read all the backlog yet, so might be missing context, but write_rtlil writes a netlist in yosys's native format | 16:45 |
| FL4SHK | jix_: that sounds like something for me to try | 16:53 |
| lofty | FL4SHK: there's also write_json | 16:56 |
| FL4SHK | lofty: I'll give that a try | 17:08 |
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| FL4SHK | what does "cells not processed" mean? | 20:28 |
| FL4SHK | it looks like even the other output types have task input ports driven with 'x | 20:29 |
| FL4SHK | I'm running yosys-nightly | 20:32 |
| FL4SHK | so I'll try another version | 20:32 |
| FL4SHK | appears to be a problem even with the Arch Linux yosys repo | 20:36 |
| FL4SHK | yosys version* | 20:36 |
| jix_ | FL4SHK: it's set by the frontend and should be cleared by the hierarchy pass and AFAIK is basically just a marker that hierarchy still has to process stuff | 20:48 |
| FL4SHK | jix_: I see | 20:49 |
| FL4SHK | do I need another pass besides `read_verilog` and `proc`? | 20:49 |
| jix_ | you should run `hierarchy` between those | 20:50 |
| FL4SHK | gotcha | 20:51 |
| FL4SHK | that explains the issue I was finding | 20:52 |
| jix_ | the list of passes in `help synth` or alternatively `help prep` are complete examples of pass orders, and taking those (or a prefix) of them is usually a good starting point if you want to do something custom | 20:52 |
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| FL4SHK | it looks like <= doesn't work | 21:07 |
| FL4SHK | but = does | 21:07 |
| FL4SHK | in a task | 21:07 |
| FL4SHK | oh wait no | 21:08 |
| FL4SHK | oh huh no it is <= that doesn't work | 21:09 |
| FL4SHK | I'm satisfied with this result | 21:21 |
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